Lines Matching defs:base_addr
56 static inline unsigned short read_rreg(u_long base_addr, u_int reg)
76 static inline unsigned short read_ireg(u_long base_addr, u_int reg)
244 write_rreg (dev->base_addr, CSR0, CSR0_BABL|CSR0_CERR|CSR0_MISS|CSR0_MERR|CSR0_TINT|CSR0_RINT|CSR0_STOP);
247 write_ireg (dev->base_addr, 5, 0x00a0); /* Receive address LED */
248 write_ireg (dev->base_addr, 6, 0x0081); /* Collision LED */
249 write_ireg (dev->base_addr, 7, 0x0090); /* XMIT LED */
250 write_ireg (dev->base_addr, 2, 0x0000); /* MODE register selects media */
253 write_rreg (dev->base_addr, i, multi_hash[i - LADRL]);
256 write_rreg (dev->base_addr, i, p[0] | (p[1] << 8));
258 write_rreg (dev->base_addr, MODE, mode);
259 write_rreg (dev->base_addr, POLLINT, 0);
260 write_rreg (dev->base_addr, SIZERXR, -RX_BUFFERS);
261 write_rreg (dev->base_addr, SIZETXR, -TX_BUFFERS);
292 write_rreg (dev->base_addr, BASERXL, priv->rxhdr);
293 write_rreg (dev->base_addr, BASERXH, 0);
294 write_rreg (dev->base_addr, BASETXL, priv->txhdr);
295 write_rreg (dev->base_addr, BASERXH, 0);
296 write_rreg (dev->base_addr, CSR0, CSR0_STOP);
297 write_rreg (dev->base_addr, CSR3, CSR3_IDONM|CSR3_BABLM|CSR3_DXSUFLO);
298 write_rreg (dev->base_addr, CSR4, CSR4_APAD_XMIT|CSR4_MFCOM|CSR4_RCVCCOM|CSR4_TXSTRTM|CSR4_JABM);
299 write_rreg (dev->base_addr, CSR0, CSR0_IENA|CSR0_STRT);
310 lnkstat = read_ireg(dev->base_addr, ISALED0) & ISALED0_LNKST;
365 write_rreg (dev->base_addr, CSR0, CSR0_STOP);
366 write_rreg (dev->base_addr, CSR3, CSR3_MASKALL);
386 stopped = read_rreg(dev->base_addr, CSR0) & CSR0_STOP;
392 write_rreg(dev->base_addr, CTRL1, CTRL1_SPND);
397 while ((read_rreg(dev->base_addr, CTRL1) & CTRL1_SPND) == 0) {
408 write_rreg(dev->base_addr, i + LADRL, multi_hash[i]);
413 write_rreg(dev->base_addr, MODE, mode);
419 write_rreg(dev->base_addr, CTRL1, 0);
461 write_rreg (dev->base_addr, CSR0, CSR0_TDMD|CSR0_IENA);
593 status = read_rreg(dev->base_addr, CSR0);
594 write_rreg(dev->base_addr, CSR0, status &
639 write_rreg (dev->base_addr, CSR0, CSR0_STOP);
640 write_rreg (dev->base_addr, CSR3, CSR3_MASKALL);
694 dev->base_addr = res->start;
704 if (!request_region(dev->base_addr, 0x18, dev->name))
710 inb(dev->base_addr + NET_RESET);
717 if (inb(dev->base_addr) != 0x08 ||
718 inb(dev->base_addr + 2) != 0x00 ||
719 inb(dev->base_addr + 4) != 0x2b)
723 dev->dev_addr[i] = inb(dev->base_addr + i * 2) & 0xff;
744 release_region(dev->base_addr, 0x18);