Lines Matching refs:csrwr32
31 csrwr32(MSGDMA_CSR_STAT_MASK, priv->rx_dma_csr,
33 csrwr32(MSGDMA_CSR_CTL_RESET, priv->rx_dma_csr,
49 csrwr32(MSGDMA_CSR_STAT_MASK, priv->rx_dma_csr, msgdma_csroffs(status));
52 csrwr32(MSGDMA_CSR_STAT_MASK, priv->tx_dma_csr,
55 csrwr32(MSGDMA_CSR_CTL_RESET, priv->tx_dma_csr,
71 csrwr32(MSGDMA_CSR_STAT_MASK, priv->tx_dma_csr, msgdma_csroffs(status));
100 csrwr32(MSGDMA_CSR_STAT_IRQ, priv->rx_dma_csr, msgdma_csroffs(status));
105 csrwr32(MSGDMA_CSR_STAT_IRQ, priv->tx_dma_csr, msgdma_csroffs(status));
111 csrwr32(lower_32_bits(buffer->dma_addr), priv->tx_dma_desc,
113 csrwr32(upper_32_bits(buffer->dma_addr), priv->tx_dma_desc,
115 csrwr32(0, priv->tx_dma_desc, msgdma_descroffs(write_addr_lo));
116 csrwr32(0, priv->tx_dma_desc, msgdma_descroffs(write_addr_hi));
117 csrwr32(buffer->len, priv->tx_dma_desc, msgdma_descroffs(len));
118 csrwr32(0, priv->tx_dma_desc, msgdma_descroffs(burst_seq_num));
119 csrwr32(MSGDMA_DESC_TX_STRIDE, priv->tx_dma_desc,
121 csrwr32(MSGDMA_DESC_CTL_TX_SINGLE, priv->tx_dma_desc,
164 csrwr32(0, priv->rx_dma_desc, msgdma_descroffs(read_addr_lo));
165 csrwr32(0, priv->rx_dma_desc, msgdma_descroffs(read_addr_hi));
166 csrwr32(lower_32_bits(dma_addr), priv->rx_dma_desc,
168 csrwr32(upper_32_bits(dma_addr), priv->rx_dma_desc,
170 csrwr32(len, priv->rx_dma_desc, msgdma_descroffs(len));
171 csrwr32(0, priv->rx_dma_desc, msgdma_descroffs(burst_seq_num));
172 csrwr32(0x00010001, priv->rx_dma_desc, msgdma_descroffs(stride));
173 csrwr32(control, priv->rx_dma_desc, msgdma_descroffs(control));