Lines Matching refs:regs_buff
2802 u32 *regs_buff = regs_data;
2813 regs_buff[num++] = tmp;
2815 regs_buff[num++] = tmp;
2817 regs_buff[num++] = tmp;
2819 regs_buff[num++] = tmp;
2821 regs_buff[num++] = tmp;
2823 regs_buff[num++] = tmp;
2825 regs_buff[num++] = tmp;
2828 regs_buff[num++] = tmp;
2831 regs_buff[num++] = tmp;
2833 regs_buff[num++] = tmp;
2835 regs_buff[num++] = tmp;
2837 regs_buff[num++] = tmp;
2839 regs_buff[num++] = tmp;
2841 regs_buff[num++] = tmp;
2843 regs_buff[num++] = tmp;
2845 regs_buff[num++] = tmp;
2848 regs_buff[num++] = tmp;
2850 regs_buff[num++] = tmp;
2852 regs_buff[num++] = tmp;
2854 regs_buff[num++] = tmp;
2856 regs_buff[num++] = tmp;
2859 regs_buff[num++] = tmp;
2861 regs_buff[num++] = tmp;
2863 regs_buff[num++] = tmp;
2865 regs_buff[num++] = tmp;
2867 regs_buff[num++] = tmp;
2869 regs_buff[num++] = tmp;
2871 regs_buff[num++] = tmp;
2873 regs_buff[num++] = tmp;
2876 regs_buff[num++] = readl(&aregs->global.txq_start_addr);
2877 regs_buff[num++] = readl(&aregs->global.txq_end_addr);
2878 regs_buff[num++] = readl(&aregs->global.rxq_start_addr);
2879 regs_buff[num++] = readl(&aregs->global.rxq_end_addr);
2880 regs_buff[num++] = readl(&aregs->global.pm_csr);
2881 regs_buff[num++] = adapter->stats.interrupt_status;
2882 regs_buff[num++] = readl(&aregs->global.int_mask);
2883 regs_buff[num++] = readl(&aregs->global.int_alias_clr_en);
2884 regs_buff[num++] = readl(&aregs->global.int_status_alias);
2885 regs_buff[num++] = readl(&aregs->global.sw_reset);
2886 regs_buff[num++] = readl(&aregs->global.slv_timer);
2887 regs_buff[num++] = readl(&aregs->global.msi_config);
2888 regs_buff[num++] = readl(&aregs->global.loopback);
2889 regs_buff[num++] = readl(&aregs->global.watchdog_timer);
2892 regs_buff[num++] = readl(&aregs->txdma.csr);
2893 regs_buff[num++] = readl(&aregs->txdma.pr_base_hi);
2894 regs_buff[num++] = readl(&aregs->txdma.pr_base_lo);
2895 regs_buff[num++] = readl(&aregs->txdma.pr_num_des);
2896 regs_buff[num++] = readl(&aregs->txdma.txq_wr_addr);
2897 regs_buff[num++] = readl(&aregs->txdma.txq_wr_addr_ext);
2898 regs_buff[num++] = readl(&aregs->txdma.txq_rd_addr);
2899 regs_buff[num++] = readl(&aregs->txdma.dma_wb_base_hi);
2900 regs_buff[num++] = readl(&aregs->txdma.dma_wb_base_lo);
2901 regs_buff[num++] = readl(&aregs->txdma.service_request);
2902 regs_buff[num++] = readl(&aregs->txdma.service_complete);
2903 regs_buff[num++] = readl(&aregs->txdma.cache_rd_index);
2904 regs_buff[num++] = readl(&aregs->txdma.cache_wr_index);
2905 regs_buff[num++] = readl(&aregs->txdma.tx_dma_error);
2906 regs_buff[num++] = readl(&aregs->txdma.desc_abort_cnt);
2907 regs_buff[num++] = readl(&aregs->txdma.payload_abort_cnt);
2908 regs_buff[num++] = readl(&aregs->txdma.writeback_abort_cnt);
2909 regs_buff[num++] = readl(&aregs->txdma.desc_timeout_cnt);
2910 regs_buff[num++] = readl(&aregs->txdma.payload_timeout_cnt);
2911 regs_buff[num++] = readl(&aregs->txdma.writeback_timeout_cnt);
2912 regs_buff[num++] = readl(&aregs->txdma.desc_error_cnt);
2913 regs_buff[num++] = readl(&aregs->txdma.payload_error_cnt);
2914 regs_buff[num++] = readl(&aregs->txdma.writeback_error_cnt);
2915 regs_buff[num++] = readl(&aregs->txdma.dropped_tlp_cnt);
2916 regs_buff[num++] = readl(&aregs->txdma.new_service_complete);
2917 regs_buff[num++] = readl(&aregs->txdma.ethernet_packet_cnt);
2920 regs_buff[num++] = readl(&aregs->rxdma.csr);
2921 regs_buff[num++] = readl(&aregs->rxdma.dma_wb_base_hi);
2922 regs_buff[num++] = readl(&aregs->rxdma.dma_wb_base_lo);
2923 regs_buff[num++] = readl(&aregs->rxdma.num_pkt_done);
2924 regs_buff[num++] = readl(&aregs->rxdma.max_pkt_time);
2925 regs_buff[num++] = readl(&aregs->rxdma.rxq_rd_addr);
2926 regs_buff[num++] = readl(&aregs->rxdma.rxq_rd_addr_ext);
2927 regs_buff[num++] = readl(&aregs->rxdma.rxq_wr_addr);
2928 regs_buff[num++] = readl(&aregs->rxdma.psr_base_hi);
2929 regs_buff[num++] = readl(&aregs->rxdma.psr_base_lo);
2930 regs_buff[num++] = readl(&aregs->rxdma.psr_num_des);
2931 regs_buff[num++] = readl(&aregs->rxdma.psr_avail_offset);
2932 regs_buff[num++] = readl(&aregs->rxdma.psr_full_offset);
2933 regs_buff[num++] = readl(&aregs->rxdma.psr_access_index);
2934 regs_buff[num++] = readl(&aregs->rxdma.psr_min_des);
2935 regs_buff[num++] = readl(&aregs->rxdma.fbr0_base_lo);
2936 regs_buff[num++] = readl(&aregs->rxdma.fbr0_base_hi);
2937 regs_buff[num++] = readl(&aregs->rxdma.fbr0_num_des);
2938 regs_buff[num++] = readl(&aregs->rxdma.fbr0_avail_offset);
2939 regs_buff[num++] = readl(&aregs->rxdma.fbr0_full_offset);
2940 regs_buff[num++] = readl(&aregs->rxdma.fbr0_rd_index);
2941 regs_buff[num++] = readl(&aregs->rxdma.fbr0_min_des);
2942 regs_buff[num++] = readl(&aregs->rxdma.fbr1_base_lo);
2943 regs_buff[num++] = readl(&aregs->rxdma.fbr1_base_hi);
2944 regs_buff[num++] = readl(&aregs->rxdma.fbr1_num_des);
2945 regs_buff[num++] = readl(&aregs->rxdma.fbr1_avail_offset);
2946 regs_buff[num++] = readl(&aregs->rxdma.fbr1_full_offset);
2947 regs_buff[num++] = readl(&aregs->rxdma.fbr1_rd_index);
2948 regs_buff[num++] = readl(&aregs->rxdma.fbr1_min_des);