Lines Matching refs:IntLatch
465 IntLatch = 0x0001, HostError = 0x0002, TxComplete = 0x0004,
1700 vp->intr_enable = SetIntrEnb | IntLatch | TxAvailable |
1706 iowrite16(AckIntr | IntLatch | TxAvailable | RxEarly | IntReq,
1897 if (ioread16(ioaddr + EL3_STATUS) & IntLatch) {
2268 if ((status & IntLatch) == 0)
2343 } while ((status = ioread16(ioaddr + EL3_CMD)) & IntLatch);
2349 iowrite16(AckIntr | IntReq | IntLatch, ioaddr + EL3_CMD);
2350 } while ((status = ioread16(ioaddr + EL3_STATUS)) & (IntLatch | RxComplete));
2386 if ((status & IntLatch) == 0)
2479 } while ((status = ioread16(ioaddr + EL3_CMD)) & IntLatch);
2485 iowrite16(AckIntr | IntReq | IntLatch, ioaddr + EL3_CMD);
2489 } while ((status = ioread16(ioaddr + EL3_STATUS)) & IntLatch);