Lines Matching defs:EL3_CMD
438 #define EL3_CMD 0x0e
441 /* The top five bits written to EL3_CMD are a command, the lower
470 CmdInProgress = 1<<12, /* EL3_CMD is still busy.*/
663 iowrite16(SelectWindow + window, vp->ioaddr + EL3_CMD);
945 iowrite16(TotalReset|0x14, ioaddr + EL3_CMD);
1492 iowrite16(cmd, ioaddr + EL3_CMD);
1625 iowrite16(SetStatusEnb | 0x00, ioaddr + EL3_CMD);
1649 iowrite16(StartCoax, ioaddr + EL3_CMD);
1659 iowrite16(StatsDisable, ioaddr + EL3_CMD);
1672 iowrite16(SetRxThreshold + (1536>>2), ioaddr + EL3_CMD);
1691 iowrite16(StatsEnable, ioaddr + EL3_CMD); /* Turn on statistics. */
1693 iowrite16(RxEnable, ioaddr + EL3_CMD); /* Enable the receiver. */
1694 iowrite16(TxEnable, ioaddr + EL3_CMD); /* Enable transmitter. */
1704 iowrite16(vp->status_enable, ioaddr + EL3_CMD);
1707 ioaddr + EL3_CMD);
1708 iowrite16(vp->intr_enable, ioaddr + EL3_CMD);
1862 ioaddr + EL3_CMD);
1877 iowrite16(FakeIntr, ioaddr + EL3_CMD);
1921 iowrite16(DownUnstall, ioaddr + EL3_CMD);
1928 iowrite16(TxEnable, ioaddr + EL3_CMD);
1971 iowrite16(TxEnable, ioaddr + EL3_CMD);
1976 iowrite16(AckIntr | RxEarly, ioaddr + EL3_CMD);
1991 ioaddr + EL3_CMD);
1997 iowrite16(vp->status_enable, ioaddr + EL3_CMD);
1998 iowrite16(vp->intr_enable, ioaddr + EL3_CMD);
2027 iowrite16(RxEnable, ioaddr + EL3_CMD); /* Re-enable the receiver. */
2028 iowrite16(AckIntr | HostError, ioaddr + EL3_CMD);
2034 iowrite16(TxEnable, ioaddr + EL3_CMD);
2067 iowrite16(StartDMADown, ioaddr + EL3_CMD);
2079 iowrite16(SetTxThreshold + (1536>>2), ioaddr + EL3_CMD);
2100 iowrite16(TxEnable, ioaddr + EL3_CMD);
2234 iowrite16(DownUnstall, ioaddr + EL3_CMD);
2298 iowrite16(AckIntr | TxAvailable, ioaddr + EL3_CMD);
2317 iowrite16(SetTxThreshold + (1536>>2), ioaddr + EL3_CMD);
2341 ioaddr + EL3_CMD);
2342 iowrite16(AckIntr | (vp->deferred & 0x7ff), ioaddr + EL3_CMD);
2343 } while ((status = ioread16(ioaddr + EL3_CMD)) & IntLatch);
2349 iowrite16(AckIntr | IntReq | IntLatch, ioaddr + EL3_CMD);
2409 iowrite16(AckIntr | UpComplete, ioaddr + EL3_CMD);
2418 iowrite16(AckIntr | DownComplete, ioaddr + EL3_CMD);
2477 ioaddr + EL3_CMD);
2478 iowrite16(AckIntr | (vp->deferred & 0x7ff), ioaddr + EL3_CMD);
2479 } while ((status = ioread16(ioaddr + EL3_CMD)) & IntLatch);
2485 iowrite16(AckIntr | IntReq | IntLatch, ioaddr + EL3_CMD);
2559 iowrite16(StartDMAUp, ioaddr + EL3_CMD);
2568 iowrite16(RxDiscard, ioaddr + EL3_CMD); /* Pop top Rx packet. */
2677 iowrite16(UpUnstall, ioaddr + EL3_CMD);
2695 iowrite16(StatsDisable, ioaddr + EL3_CMD);
2698 iowrite16(RxDisable, ioaddr + EL3_CMD);
2699 iowrite16(TxDisable, ioaddr + EL3_CMD);
2706 iowrite16(StopCoax, ioaddr + EL3_CMD);
2708 iowrite16(SetIntrEnb | 0x0000, ioaddr + EL3_CMD);
2817 iowrite16(DownUnstall, ioaddr + EL3_CMD);
3067 iowrite16(new_mode, ioaddr + EL3_CMD);
3235 iowrite16(SetRxFilter|RxStation|RxMulticast|RxBroadcast, ioaddr + EL3_CMD);
3236 iowrite16(RxEnable, ioaddr + EL3_CMD);
3278 vp->ioaddr + EL3_CMD);
3336 iowrite16(TotalReset, ioaddr + EL3_CMD);