Lines Matching refs:chip
16 #include "chip.h"
20 int mv88e6xxx_port_read(struct mv88e6xxx_chip *chip, int port, int reg,
23 int addr = chip->info->port_base_addr + port;
25 return mv88e6xxx_read(chip, addr, reg, val);
28 int mv88e6xxx_port_write(struct mv88e6xxx_chip *chip, int port, int reg,
31 int addr = chip->info->port_base_addr + port;
33 return mv88e6xxx_write(chip, addr, reg, val);
41 int mv88e6185_port_set_pause(struct mv88e6xxx_chip *chip, int port,
47 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®);
56 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_STS, reg);
68 static int mv88e6xxx_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port,
74 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, ®);
98 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg);
102 dev_dbg(chip->dev, "p%d: delay RXCLK %s, TXCLK %s\n", port,
109 int mv88e6352_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port,
115 return mv88e6xxx_port_set_rgmii_delay(chip, port, mode);
118 int mv88e6390_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port,
124 return mv88e6xxx_port_set_rgmii_delay(chip, port, mode);
127 int mv88e6xxx_port_set_link(struct mv88e6xxx_chip *chip, int port, int link)
132 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, ®);
154 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg);
158 dev_dbg(chip->dev, "p%d: %s link %s\n", port,
165 static int mv88e6xxx_port_set_speed_duplex(struct mv88e6xxx_chip *chip,
220 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, ®);
237 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg);
242 dev_dbg(chip->dev, "p%d: Speed set to %d Mbps\n", port, speed);
244 dev_dbg(chip->dev, "p%d: Speed unforced\n", port);
245 dev_dbg(chip->dev, "p%d: %s %s duplex\n", port,
253 int mv88e6065_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port,
263 return mv88e6xxx_port_set_speed_duplex(chip, port, speed, false, false,
268 int mv88e6185_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port,
277 return mv88e6xxx_port_set_speed_duplex(chip, port, speed, false, false,
282 int mv88e6250_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port,
291 return mv88e6xxx_port_set_speed_duplex(chip, port, speed, false, false,
296 int mv88e6341_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port,
311 return mv88e6xxx_port_set_speed_duplex(chip, port, speed, !port, true,
324 int mv88e6352_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port,
336 return mv88e6xxx_port_set_speed_duplex(chip, port, speed, true, false,
341 int mv88e6390_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port,
356 return mv88e6xxx_port_set_speed_duplex(chip, port, speed, true, true,
369 int mv88e6390x_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port,
381 return mv88e6xxx_port_set_speed_duplex(chip, port, speed, true, true,
393 static int mv88e6xxx_port_set_cmode(struct mv88e6xxx_chip *chip, int port,
429 if (cmode == chip->ports[port].cmode && !force)
432 lane = mv88e6xxx_serdes_get_lane(chip, port);
434 if (chip->ports[port].serdes_irq) {
435 err = mv88e6xxx_serdes_irq_disable(chip, port, lane);
440 err = mv88e6xxx_serdes_power_down(chip, port, lane);
445 chip->ports[port].cmode = 0;
448 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®);
455 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_STS, reg);
459 chip->ports[port].cmode = cmode;
461 lane = mv88e6xxx_serdes_get_lane(chip, port);
465 err = mv88e6xxx_serdes_power_up(chip, port, lane);
469 if (chip->ports[port].serdes_irq) {
470 err = mv88e6xxx_serdes_irq_enable(chip, port, lane);
479 int mv88e6390x_port_set_cmode(struct mv88e6xxx_chip *chip, int port,
485 return mv88e6xxx_port_set_cmode(chip, port, mode, false);
488 int mv88e6390_port_set_cmode(struct mv88e6xxx_chip *chip, int port,
505 return mv88e6xxx_port_set_cmode(chip, port, mode, false);
508 static int mv88e6341_port_set_cmode_writable(struct mv88e6xxx_chip *chip,
517 addr = chip->info->port_base_addr + port;
519 err = mv88e6xxx_port_hidden_read(chip, 0x7, addr, 0, ®);
530 return mv88e6xxx_port_hidden_write(chip, 0x7, addr, 0, reg);
533 int mv88e6341_port_set_cmode(struct mv88e6xxx_chip *chip, int port,
552 err = mv88e6341_port_set_cmode_writable(chip, port);
556 return mv88e6xxx_port_set_cmode(chip, port, mode, true);
559 int mv88e6185_port_get_cmode(struct mv88e6xxx_chip *chip, int port, u8 *cmode)
564 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®);
573 int mv88e6352_port_get_cmode(struct mv88e6xxx_chip *chip, int port, u8 *cmode)
578 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®);
593 int mv88e6097_port_pause_limit(struct mv88e6xxx_chip *chip, int port, u8 in,
596 return mv88e6xxx_port_write(chip, port, MV88E6097_PORT_JAM_CTL,
600 int mv88e6390_port_pause_limit(struct mv88e6xxx_chip *chip, int port, u8 in,
605 err = mv88e6xxx_port_write(chip, port, MV88E6390_PORT_FLOW_CTL,
611 return mv88e6xxx_port_write(chip, port, MV88E6390_PORT_FLOW_CTL,
625 int mv88e6xxx_port_set_state(struct mv88e6xxx_chip *chip, int port, u8 state)
630 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®);
656 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
660 dev_dbg(chip->dev, "p%d: PortState set to %s\n", port,
666 int mv88e6xxx_port_set_egress_mode(struct mv88e6xxx_chip *chip, int port,
672 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®);
695 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
698 int mv88e6085_port_set_frame_mode(struct mv88e6xxx_chip *chip, int port,
704 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®);
721 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
724 int mv88e6351_port_set_frame_mode(struct mv88e6xxx_chip *chip, int port,
730 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®);
753 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
756 static int mv88e6185_port_set_forward_unknown(struct mv88e6xxx_chip *chip,
762 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®);
771 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
774 int mv88e6352_port_set_egress_floods(struct mv88e6xxx_chip *chip, int port,
780 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®);
795 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
800 int mv88e6xxx_port_set_message_port(struct mv88e6xxx_chip *chip, int port,
806 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL1, &val);
815 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL1, val);
820 int mv88e6xxx_port_set_vlan_map(struct mv88e6xxx_chip *chip, int port, u16 map)
822 const u16 mask = mv88e6xxx_port_mask(chip);
826 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_BASE_VLAN, ®);
833 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_BASE_VLAN, reg);
837 dev_dbg(chip->dev, "p%d: VLANTable set to %.3x\n", port, map);
842 int mv88e6xxx_port_get_fid(struct mv88e6xxx_chip *chip, int port, u16 *fid)
844 const u16 upper_mask = (mv88e6xxx_num_databases(chip) - 1) >> 4;
849 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_BASE_VLAN, ®);
857 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL1,
868 int mv88e6xxx_port_set_fid(struct mv88e6xxx_chip *chip, int port, u16 fid)
870 const u16 upper_mask = (mv88e6xxx_num_databases(chip) - 1) >> 4;
874 if (fid >= mv88e6xxx_num_databases(chip))
878 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_BASE_VLAN, ®);
885 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_BASE_VLAN, reg);
891 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL1,
899 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL1,
905 dev_dbg(chip->dev, "p%d: FID set to %u\n", port, fid);
912 int mv88e6xxx_port_get_pvid(struct mv88e6xxx_chip *chip, int port, u16 *pvid)
917 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN,
927 int mv88e6xxx_port_set_pvid(struct mv88e6xxx_chip *chip, int port, u16 pvid)
932 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN,
940 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN,
945 dev_dbg(chip->dev, "p%d: DefaultVID set to %u\n", port, pvid);
959 static int mv88e6185_port_set_default_forward(struct mv88e6xxx_chip *chip,
965 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®);
974 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg);
977 int mv88e6185_port_set_egress_floods(struct mv88e6xxx_chip *chip, int port,
982 err = mv88e6185_port_set_forward_unknown(chip, port, unicast);
986 return mv88e6185_port_set_default_forward(chip, port, multicast);
989 int mv88e6095_port_set_upstream_port(struct mv88e6xxx_chip *chip, int port,
995 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®);
1002 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg);
1005 int mv88e6xxx_port_set_mirror(struct mv88e6xxx_chip *chip, int port,
1014 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®);
1021 mirror_port = &chip->ports[port].mirror_ingress;
1025 mirror_port = &chip->ports[port].mirror_egress;
1035 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg);
1042 int mv88e6xxx_port_set_8021q_mode(struct mv88e6xxx_chip *chip, int port,
1048 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®);
1055 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg);
1059 dev_dbg(chip->dev, "p%d: 802.1QMode set to %s\n", port,
1065 int mv88e6xxx_port_set_map_da(struct mv88e6xxx_chip *chip, int port)
1070 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®);
1076 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg);
1079 int mv88e6165_port_set_jumbo_size(struct mv88e6xxx_chip *chip, int port,
1087 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®);
1102 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg);
1107 int mv88e6095_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port)
1109 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL1,
1113 int mv88e6097_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port)
1115 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL1,
1121 int mv88e6xxx_port_disable_learn_limit(struct mv88e6xxx_chip *chip, int port)
1123 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ATU_CTL, 0);
1128 int mv88e6xxx_port_disable_pri_override(struct mv88e6xxx_chip *chip, int port)
1130 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_PRI_OVERRIDE, 0);
1135 int mv88e6351_port_set_ether_type(struct mv88e6xxx_chip *chip, int port,
1138 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ETH_TYPE, etype);
1145 int mv88e6095_port_tag_remap(struct mv88e6xxx_chip *chip, int port)
1150 err = mv88e6xxx_port_write(chip, port,
1156 return mv88e6xxx_port_write(chip, port,
1161 static int mv88e6xxx_port_ieeepmt_write(struct mv88e6xxx_chip *chip,
1170 return mv88e6xxx_port_write(chip, port,
1174 int mv88e6390_port_tag_remap(struct mv88e6xxx_chip *chip, int port)
1181 err = mv88e6xxx_port_ieeepmt_write(chip, port, table, i,
1187 err = mv88e6xxx_port_ieeepmt_write(chip, port, table, i, i);
1192 err = mv88e6xxx_port_ieeepmt_write(chip, port, table, i, i);
1197 err = mv88e6xxx_port_ieeepmt_write(chip, port, table, i, i);
1207 int mv88e6352_port_set_policy(struct mv88e6xxx_chip *chip, int port,
1269 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_POLICY_CTL, ®);
1276 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_POLICY_CTL, reg);