Lines Matching refs:chip
15 #include "chip.h"
19 int mv88e6xxx_g2_read(struct mv88e6xxx_chip *chip, int reg, u16 *val)
21 return mv88e6xxx_read(chip, chip->info->global2_addr, reg, val);
24 int mv88e6xxx_g2_write(struct mv88e6xxx_chip *chip, int reg, u16 val)
26 return mv88e6xxx_write(chip, chip->info->global2_addr, reg, val);
29 int mv88e6xxx_g2_wait_bit(struct mv88e6xxx_chip *chip, int reg, int
32 return mv88e6xxx_wait_bit(chip, chip->info->global2_addr, reg,
38 static int mv88e6xxx_g2_int_source(struct mv88e6xxx_chip *chip, u16 *src)
41 return mv88e6xxx_g2_read(chip, MV88E6XXX_G2_INT_SRC, src);
46 static int mv88e6xxx_g2_int_mask(struct mv88e6xxx_chip *chip, u16 mask)
48 return mv88e6xxx_g2_write(chip, MV88E6XXX_G2_INT_MASK, mask);
53 static int mv88e6xxx_g2_mgmt_enable_2x(struct mv88e6xxx_chip *chip, u16 en2x)
55 return mv88e6xxx_g2_write(chip, MV88E6XXX_G2_MGMT_EN_2X, en2x);
60 static int mv88e6xxx_g2_mgmt_enable_0x(struct mv88e6xxx_chip *chip, u16 en0x)
62 return mv88e6xxx_g2_write(chip, MV88E6XXX_G2_MGMT_EN_0X, en0x);
67 static int mv88e6xxx_g2_switch_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip,
73 err = mv88e6xxx_g2_read(chip, MV88E6XXX_G2_SWITCH_MGMT, &val);
82 return mv88e6xxx_g2_write(chip, MV88E6XXX_G2_SWITCH_MGMT, val);
85 int mv88e6185_g2_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip)
92 err = mv88e6xxx_g2_mgmt_enable_0x(chip, 0xffff);
96 return mv88e6xxx_g2_switch_mgmt_rsvd2cpu(chip, true);
99 int mv88e6352_g2_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip)
106 err = mv88e6xxx_g2_mgmt_enable_2x(chip, 0xffff);
110 return mv88e6185_g2_mgmt_rsvd2cpu(chip);
115 int mv88e6xxx_g2_device_mapping_write(struct mv88e6xxx_chip *chip, int target,
123 return mv88e6xxx_g2_write(chip, MV88E6XXX_G2_DEVICE_MAPPING,
129 static int mv88e6xxx_g2_trunk_mask_write(struct mv88e6xxx_chip *chip, int num,
132 u16 val = (num << 12) | (mask & mv88e6xxx_port_mask(chip));
137 return mv88e6xxx_g2_write(chip, MV88E6XXX_G2_TRUNK_MASK,
143 static int mv88e6xxx_g2_trunk_mapping_write(struct mv88e6xxx_chip *chip, int id,
146 const u16 port_mask = BIT(mv88e6xxx_num_ports(chip)) - 1;
149 return mv88e6xxx_g2_write(chip, MV88E6XXX_G2_TRUNK_MAPPING,
153 int mv88e6xxx_g2_trunk_clear(struct mv88e6xxx_chip *chip)
155 const u16 port_mask = BIT(mv88e6xxx_num_ports(chip)) - 1;
160 err = mv88e6xxx_g2_trunk_mask_write(chip, i, false, port_mask);
167 err = mv88e6xxx_g2_trunk_mapping_write(chip, i, 0);
179 static int mv88e6xxx_g2_irl_wait(struct mv88e6xxx_chip *chip)
183 return mv88e6xxx_g2_wait_bit(chip, MV88E6XXX_G2_IRL_CMD, bit, 0);
186 static int mv88e6xxx_g2_irl_op(struct mv88e6xxx_chip *chip, u16 op, int port,
191 err = mv88e6xxx_g2_write(chip, MV88E6XXX_G2_IRL_CMD,
197 return mv88e6xxx_g2_irl_wait(chip);
200 int mv88e6352_g2_irl_init_all(struct mv88e6xxx_chip *chip, int port)
202 return mv88e6xxx_g2_irl_op(chip, MV88E6352_G2_IRL_CMD_OP_INIT_ALL, port,
206 int mv88e6390_g2_irl_init_all(struct mv88e6xxx_chip *chip, int port)
208 return mv88e6xxx_g2_irl_op(chip, MV88E6390_G2_IRL_CMD_OP_INIT_ALL, port,
212 /* Offset 0x0B: Cross-chip Port VLAN (Addr) Register
213 * Offset 0x0C: Cross-chip Port VLAN Data Register
216 static int mv88e6xxx_g2_pvt_op_wait(struct mv88e6xxx_chip *chip)
220 return mv88e6xxx_g2_wait_bit(chip, MV88E6XXX_G2_PVT_ADDR, bit, 0);
223 static int mv88e6xxx_g2_pvt_op(struct mv88e6xxx_chip *chip, int src_dev,
228 /* 9-bit Cross-chip PVT pointer: with MV88E6XXX_G2_MISC_5_BIT_PORT
235 err = mv88e6xxx_g2_write(chip, MV88E6XXX_G2_PVT_ADDR, op);
239 return mv88e6xxx_g2_pvt_op_wait(chip);
242 int mv88e6xxx_g2_pvt_write(struct mv88e6xxx_chip *chip, int src_dev,
247 err = mv88e6xxx_g2_pvt_op_wait(chip);
251 err = mv88e6xxx_g2_write(chip, MV88E6XXX_G2_PVT_DATA, data);
255 return mv88e6xxx_g2_pvt_op(chip, src_dev, src_port,
261 static int mv88e6xxx_g2_switch_mac_write(struct mv88e6xxx_chip *chip,
266 return mv88e6xxx_g2_write(chip, MV88E6XXX_G2_SWITCH_MAC,
270 int mv88e6xxx_g2_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr)
275 err = mv88e6xxx_g2_switch_mac_write(chip, i, addr[i]);
285 int mv88e6xxx_g2_atu_stats_set(struct mv88e6xxx_chip *chip, u16 kind, u16 bin)
287 return mv88e6xxx_g2_write(chip, MV88E6XXX_G2_ATU_STATS,
291 int mv88e6xxx_g2_atu_stats_get(struct mv88e6xxx_chip *chip, u16 *stats)
293 return mv88e6xxx_g2_read(chip, MV88E6XXX_G2_ATU_STATS, stats);
298 static int mv88e6xxx_g2_pot_write(struct mv88e6xxx_chip *chip, int pointer,
303 return mv88e6xxx_g2_write(chip, MV88E6XXX_G2_PRIO_OVERRIDE,
307 int mv88e6xxx_g2_pot_clear(struct mv88e6xxx_chip *chip)
313 err = mv88e6xxx_g2_pot_write(chip, i, 0);
326 int mv88e6xxx_g2_eeprom_wait(struct mv88e6xxx_chip *chip)
331 err = mv88e6xxx_g2_wait_bit(chip, MV88E6XXX_G2_EEPROM_CMD, bit, 0);
337 return mv88e6xxx_g2_wait_bit(chip, MV88E6XXX_G2_EEPROM_CMD, bit, 0);
340 static int mv88e6xxx_g2_eeprom_cmd(struct mv88e6xxx_chip *chip, u16 cmd)
344 err = mv88e6xxx_g2_write(chip, MV88E6XXX_G2_EEPROM_CMD,
349 return mv88e6xxx_g2_eeprom_wait(chip);
352 static int mv88e6xxx_g2_eeprom_read8(struct mv88e6xxx_chip *chip,
358 err = mv88e6xxx_g2_eeprom_wait(chip);
362 err = mv88e6xxx_g2_write(chip, MV88E6390_G2_EEPROM_ADDR, addr);
366 err = mv88e6xxx_g2_eeprom_cmd(chip, cmd);
370 err = mv88e6xxx_g2_read(chip, MV88E6XXX_G2_EEPROM_CMD, &cmd);
379 static int mv88e6xxx_g2_eeprom_write8(struct mv88e6xxx_chip *chip,
386 err = mv88e6xxx_g2_eeprom_wait(chip);
390 err = mv88e6xxx_g2_write(chip, MV88E6390_G2_EEPROM_ADDR, addr);
394 return mv88e6xxx_g2_eeprom_cmd(chip, cmd | data);
397 static int mv88e6xxx_g2_eeprom_read16(struct mv88e6xxx_chip *chip,
403 err = mv88e6xxx_g2_eeprom_wait(chip);
407 err = mv88e6xxx_g2_eeprom_cmd(chip, cmd);
411 return mv88e6xxx_g2_read(chip, MV88E6352_G2_EEPROM_DATA, data);
414 static int mv88e6xxx_g2_eeprom_write16(struct mv88e6xxx_chip *chip,
420 err = mv88e6xxx_g2_eeprom_wait(chip);
424 err = mv88e6xxx_g2_write(chip, MV88E6352_G2_EEPROM_DATA, data);
428 return mv88e6xxx_g2_eeprom_cmd(chip, cmd);
431 int mv88e6xxx_g2_get_eeprom8(struct mv88e6xxx_chip *chip,
441 err = mv88e6xxx_g2_eeprom_read8(chip, offset, data);
454 int mv88e6xxx_g2_set_eeprom8(struct mv88e6xxx_chip *chip,
464 err = mv88e6xxx_g2_eeprom_write8(chip, offset, *data);
477 int mv88e6xxx_g2_get_eeprom16(struct mv88e6xxx_chip *chip,
488 err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val);
500 err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val);
513 err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val);
527 int mv88e6xxx_g2_set_eeprom16(struct mv88e6xxx_chip *chip,
536 err = mv88e6xxx_g2_read(chip, MV88E6XXX_G2_EEPROM_CMD, &val);
546 err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val);
552 err = mv88e6xxx_g2_eeprom_write16(chip, offset >> 1, val);
565 err = mv88e6xxx_g2_eeprom_write16(chip, offset >> 1, val);
575 err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val);
581 err = mv88e6xxx_g2_eeprom_write16(chip, offset >> 1, val);
597 static int mv88e6xxx_g2_smi_phy_wait(struct mv88e6xxx_chip *chip)
601 return mv88e6xxx_g2_wait_bit(chip, MV88E6XXX_G2_SMI_PHY_CMD, bit, 0);
604 static int mv88e6xxx_g2_smi_phy_cmd(struct mv88e6xxx_chip *chip, u16 cmd)
608 err = mv88e6xxx_g2_write(chip, MV88E6XXX_G2_SMI_PHY_CMD,
613 return mv88e6xxx_g2_smi_phy_wait(chip);
616 static int mv88e6xxx_g2_smi_phy_access(struct mv88e6xxx_chip *chip,
636 return mv88e6xxx_g2_smi_phy_cmd(chip, cmd);
639 static int mv88e6xxx_g2_smi_phy_access_c22(struct mv88e6xxx_chip *chip,
643 return mv88e6xxx_g2_smi_phy_access(chip, external, false, op, dev, reg);
647 static int mv88e6xxx_g2_smi_phy_read_data_c22(struct mv88e6xxx_chip *chip,
654 err = mv88e6xxx_g2_smi_phy_wait(chip);
658 err = mv88e6xxx_g2_smi_phy_access_c22(chip, external, op, dev, reg);
662 return mv88e6xxx_g2_read(chip, MV88E6XXX_G2_SMI_PHY_DATA, data);
666 static int mv88e6xxx_g2_smi_phy_write_data_c22(struct mv88e6xxx_chip *chip,
673 err = mv88e6xxx_g2_smi_phy_wait(chip);
677 err = mv88e6xxx_g2_write(chip, MV88E6XXX_G2_SMI_PHY_DATA, data);
681 return mv88e6xxx_g2_smi_phy_access_c22(chip, external, op, dev, reg);
684 static int mv88e6xxx_g2_smi_phy_access_c45(struct mv88e6xxx_chip *chip,
688 return mv88e6xxx_g2_smi_phy_access(chip, external, true, op, port, dev);
692 static int mv88e6xxx_g2_smi_phy_write_addr_c45(struct mv88e6xxx_chip *chip,
699 err = mv88e6xxx_g2_smi_phy_wait(chip);
703 err = mv88e6xxx_g2_write(chip, MV88E6XXX_G2_SMI_PHY_DATA, addr);
707 return mv88e6xxx_g2_smi_phy_access_c45(chip, external, op, port, dev);
711 static int mv88e6xxx_g2_smi_phy_read_data_c45(struct mv88e6xxx_chip *chip,
718 err = mv88e6xxx_g2_smi_phy_access_c45(chip, external, op, port, dev);
722 return mv88e6xxx_g2_read(chip, MV88E6XXX_G2_SMI_PHY_DATA, data);
725 static int mv88e6xxx_g2_smi_phy_read_c45(struct mv88e6xxx_chip *chip,
733 err = mv88e6xxx_g2_smi_phy_write_addr_c45(chip, external, port, dev,
738 return mv88e6xxx_g2_smi_phy_read_data_c45(chip, external, port, dev,
743 static int mv88e6xxx_g2_smi_phy_write_data_c45(struct mv88e6xxx_chip *chip,
750 err = mv88e6xxx_g2_write(chip, MV88E6XXX_G2_SMI_PHY_DATA, data);
754 return mv88e6xxx_g2_smi_phy_access_c45(chip, external, op, port, dev);
757 static int mv88e6xxx_g2_smi_phy_write_c45(struct mv88e6xxx_chip *chip,
765 err = mv88e6xxx_g2_smi_phy_write_addr_c45(chip, external, port, dev,
770 return mv88e6xxx_g2_smi_phy_write_data_c45(chip, external, port, dev,
774 int mv88e6xxx_g2_smi_phy_read(struct mv88e6xxx_chip *chip, struct mii_bus *bus,
781 return mv88e6xxx_g2_smi_phy_read_c45(chip, external, addr, reg,
784 return mv88e6xxx_g2_smi_phy_read_data_c22(chip, external, addr, reg,
788 int mv88e6xxx_g2_smi_phy_write(struct mv88e6xxx_chip *chip, struct mii_bus *bus,
795 return mv88e6xxx_g2_smi_phy_write_c45(chip, external, addr, reg,
798 return mv88e6xxx_g2_smi_phy_write_data_c22(chip, external, addr, reg,
803 static int mv88e6097_watchdog_action(struct mv88e6xxx_chip *chip, int irq)
807 mv88e6xxx_g2_read(chip, MV88E6352_G2_WDOG_CTL, ®);
809 dev_info(chip->dev, "Watchdog event: 0x%04x", reg);
814 static void mv88e6097_watchdog_free(struct mv88e6xxx_chip *chip)
818 mv88e6xxx_g2_read(chip, MV88E6352_G2_WDOG_CTL, ®);
823 mv88e6xxx_g2_write(chip, MV88E6352_G2_WDOG_CTL, reg);
826 static int mv88e6097_watchdog_setup(struct mv88e6xxx_chip *chip)
828 return mv88e6xxx_g2_write(chip, MV88E6352_G2_WDOG_CTL,
840 static void mv88e6250_watchdog_free(struct mv88e6xxx_chip *chip)
844 mv88e6xxx_g2_read(chip, MV88E6250_G2_WDOG_CTL, ®);
849 mv88e6xxx_g2_write(chip, MV88E6250_G2_WDOG_CTL, reg);
852 static int mv88e6250_watchdog_setup(struct mv88e6xxx_chip *chip)
854 return mv88e6xxx_g2_write(chip, MV88E6250_G2_WDOG_CTL,
866 static int mv88e6390_watchdog_setup(struct mv88e6xxx_chip *chip)
868 return mv88e6xxx_g2_write(chip, MV88E6390_G2_WDOG_CTL,
877 static int mv88e6390_watchdog_action(struct mv88e6xxx_chip *chip, int irq)
881 mv88e6xxx_g2_write(chip, MV88E6390_G2_WDOG_CTL,
883 mv88e6xxx_g2_read(chip, MV88E6390_G2_WDOG_CTL, ®);
885 dev_info(chip->dev, "Watchdog event: 0x%04x",
888 mv88e6xxx_g2_write(chip, MV88E6390_G2_WDOG_CTL,
890 mv88e6xxx_g2_read(chip, MV88E6390_G2_WDOG_CTL, ®);
892 dev_info(chip->dev, "Watchdog history: 0x%04x",
896 if (chip->info->ops->reset)
897 chip->info->ops->reset(chip);
899 mv88e6390_watchdog_setup(chip);
904 static void mv88e6390_watchdog_free(struct mv88e6xxx_chip *chip)
906 mv88e6xxx_g2_write(chip, MV88E6390_G2_WDOG_CTL,
919 struct mv88e6xxx_chip *chip = dev_id;
922 mv88e6xxx_reg_lock(chip);
923 if (chip->info->ops->watchdog_ops->irq_action)
924 ret = chip->info->ops->watchdog_ops->irq_action(chip, irq);
925 mv88e6xxx_reg_unlock(chip);
930 static void mv88e6xxx_g2_watchdog_free(struct mv88e6xxx_chip *chip)
932 mv88e6xxx_reg_lock(chip);
933 if (chip->info->ops->watchdog_ops->irq_free)
934 chip->info->ops->watchdog_ops->irq_free(chip);
935 mv88e6xxx_reg_unlock(chip);
937 free_irq(chip->watchdog_irq, chip);
938 irq_dispose_mapping(chip->watchdog_irq);
941 static int mv88e6xxx_g2_watchdog_setup(struct mv88e6xxx_chip *chip)
945 chip->watchdog_irq = irq_find_mapping(chip->g2_irq.domain,
947 if (chip->watchdog_irq < 0)
948 return chip->watchdog_irq;
950 snprintf(chip->watchdog_irq_name, sizeof(chip->watchdog_irq_name),
951 "mv88e6xxx-%s-watchdog", dev_name(chip->dev));
953 err = request_threaded_irq(chip->watchdog_irq, NULL,
956 chip->watchdog_irq_name, chip);
960 mv88e6xxx_reg_lock(chip);
961 if (chip->info->ops->watchdog_ops->irq_setup)
962 err = chip->info->ops->watchdog_ops->irq_setup(chip);
963 mv88e6xxx_reg_unlock(chip);
970 static int mv88e6xxx_g2_misc_5_bit_port(struct mv88e6xxx_chip *chip,
976 err = mv88e6xxx_g2_read(chip, MV88E6XXX_G2_MISC, &val);
985 return mv88e6xxx_g2_write(chip, MV88E6XXX_G2_MISC, val);
988 int mv88e6xxx_g2_misc_4_bit_port(struct mv88e6xxx_chip *chip)
990 return mv88e6xxx_g2_misc_5_bit_port(chip, false);
995 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
998 chip->g2_irq.masked |= (1 << n);
1003 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
1006 chip->g2_irq.masked &= ~(1 << n);
1011 struct mv88e6xxx_chip *chip = dev_id;
1018 mv88e6xxx_reg_lock(chip);
1019 err = mv88e6xxx_g2_int_source(chip, ®);
1020 mv88e6xxx_reg_unlock(chip);
1026 sub_irq = irq_find_mapping(chip->g2_irq.domain, n);
1037 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
1039 mv88e6xxx_reg_lock(chip);
1044 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
1047 err = mv88e6xxx_g2_int_mask(chip, ~chip->g2_irq.masked);
1049 dev_err(chip->dev, "failed to mask interrupts\n");
1051 mv88e6xxx_reg_unlock(chip);
1066 struct mv88e6xxx_chip *chip = d->host_data;
1069 irq_set_chip_and_handler(irq, &chip->g2_irq.chip, handle_level_irq);
1080 void mv88e6xxx_g2_irq_free(struct mv88e6xxx_chip *chip)
1084 mv88e6xxx_g2_watchdog_free(chip);
1086 free_irq(chip->device_irq, chip);
1087 irq_dispose_mapping(chip->device_irq);
1090 virq = irq_find_mapping(chip->g2_irq.domain, irq);
1094 irq_domain_remove(chip->g2_irq.domain);
1097 int mv88e6xxx_g2_irq_setup(struct mv88e6xxx_chip *chip)
1101 chip->g2_irq.masked = ~0;
1102 mv88e6xxx_reg_lock(chip);
1103 err = mv88e6xxx_g2_int_mask(chip, ~chip->g2_irq.masked);
1104 mv88e6xxx_reg_unlock(chip);
1108 chip->g2_irq.domain = irq_domain_add_simple(
1109 chip->dev->of_node, 16, 0, &mv88e6xxx_g2_irq_domain_ops, chip);
1110 if (!chip->g2_irq.domain)
1114 irq_create_mapping(chip->g2_irq.domain, irq);
1116 chip->g2_irq.chip = mv88e6xxx_g2_irq_chip;
1118 chip->device_irq = irq_find_mapping(chip->g1_irq.domain,
1120 if (chip->device_irq < 0) {
1121 err = chip->device_irq;
1125 snprintf(chip->device_irq_name, sizeof(chip->device_irq_name),
1126 "mv88e6xxx-%s-g2", dev_name(chip->dev));
1128 err = request_threaded_irq(chip->device_irq, NULL,
1130 IRQF_ONESHOT, chip->device_irq_name, chip);
1134 return mv88e6xxx_g2_watchdog_setup(chip);
1138 virq = irq_find_mapping(chip->g2_irq.domain, irq);
1142 irq_domain_remove(chip->g2_irq.domain);
1147 int mv88e6xxx_g2_irq_mdio_setup(struct mv88e6xxx_chip *chip,
1152 for (phy = 0; phy < chip->info->num_internal_phys; phy++) {
1153 irq = irq_find_mapping(chip->g2_irq.domain, phy);
1158 bus->irq[chip->info->phy_base_addr + phy] = irq;
1170 void mv88e6xxx_g2_irq_mdio_free(struct mv88e6xxx_chip *chip,
1175 for (phy = 0; phy < chip->info->num_internal_phys; phy++)