Lines Matching refs:chip
13 #include "chip.h"
18 static int mv88e6xxx_g1_atu_fid_write(struct mv88e6xxx_chip *chip, u16 fid)
20 return mv88e6xxx_g1_write(chip, MV88E6352_G1_ATU_FID, fid & 0xfff);
25 int mv88e6xxx_g1_atu_set_learn2all(struct mv88e6xxx_chip *chip, bool learn2all)
30 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_ATU_CTL, &val);
39 return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_ATU_CTL, val);
42 int mv88e6xxx_g1_atu_set_age_time(struct mv88e6xxx_chip *chip,
45 const unsigned int coeff = chip->info->age_time_coeff;
58 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_ATU_CTL, &val);
66 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_ATU_CTL, val);
70 dev_dbg(chip->dev, "AgeTime set to 0x%02x (%d ms)\n", age_time,
76 int mv88e6165_g1_atu_get_hash(struct mv88e6xxx_chip *chip, u8 *hash)
81 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_ATU_CTL, &val);
90 int mv88e6165_g1_atu_set_hash(struct mv88e6xxx_chip *chip, u8 hash)
98 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_ATU_CTL, &val);
105 return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_ATU_CTL, val);
110 static int mv88e6xxx_g1_atu_op_wait(struct mv88e6xxx_chip *chip)
114 return mv88e6xxx_g1_wait_bit(chip, MV88E6XXX_G1_ATU_OP, bit, 0);
117 static int mv88e6xxx_g1_atu_op(struct mv88e6xxx_chip *chip, u16 fid, u16 op)
123 if (mv88e6xxx_num_databases(chip) > 256) {
124 err = mv88e6xxx_g1_atu_fid_write(chip, fid);
128 if (mv88e6xxx_num_databases(chip) > 64) {
130 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_ATU_CTL,
136 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_ATU_CTL,
140 } else if (mv88e6xxx_num_databases(chip) > 16) {
149 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_ATU_OP,
154 return mv88e6xxx_g1_atu_op_wait(chip);
157 int mv88e6xxx_g1_atu_get_next(struct mv88e6xxx_chip *chip, u16 fid)
159 return mv88e6xxx_g1_atu_op(chip, fid, MV88E6XXX_G1_ATU_OP_GET_NEXT_DB);
164 static int mv88e6xxx_g1_atu_data_read(struct mv88e6xxx_chip *chip,
170 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_ATU_DATA, &val);
177 entry->portvec = (val >> 4) & mv88e6xxx_port_mask(chip);
183 static int mv88e6xxx_g1_atu_data_write(struct mv88e6xxx_chip *chip,
192 data |= (entry->portvec & mv88e6xxx_port_mask(chip)) << 4;
195 return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_ATU_DATA, data);
203 static int mv88e6xxx_g1_atu_mac_read(struct mv88e6xxx_chip *chip,
210 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_ATU_MAC01 + i, &val);
221 static int mv88e6xxx_g1_atu_mac_write(struct mv88e6xxx_chip *chip,
229 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_ATU_MAC01 + i, val);
239 int mv88e6xxx_g1_atu_getnext(struct mv88e6xxx_chip *chip, u16 fid,
244 err = mv88e6xxx_g1_atu_op_wait(chip);
250 err = mv88e6xxx_g1_atu_mac_write(chip, entry);
255 err = mv88e6xxx_g1_atu_op(chip, fid, MV88E6XXX_G1_ATU_OP_GET_NEXT_DB);
259 err = mv88e6xxx_g1_atu_data_read(chip, entry);
263 return mv88e6xxx_g1_atu_mac_read(chip, entry);
266 int mv88e6xxx_g1_atu_loadpurge(struct mv88e6xxx_chip *chip, u16 fid,
271 err = mv88e6xxx_g1_atu_op_wait(chip);
275 err = mv88e6xxx_g1_atu_mac_write(chip, entry);
279 err = mv88e6xxx_g1_atu_data_write(chip, entry);
283 return mv88e6xxx_g1_atu_op(chip, fid, MV88E6XXX_G1_ATU_OP_LOAD_DB);
286 static int mv88e6xxx_g1_atu_flushmove(struct mv88e6xxx_chip *chip, u16 fid,
293 err = mv88e6xxx_g1_atu_op_wait(chip);
297 err = mv88e6xxx_g1_atu_data_write(chip, entry);
311 return mv88e6xxx_g1_atu_op(chip, fid, op);
314 int mv88e6xxx_g1_atu_flush(struct mv88e6xxx_chip *chip, u16 fid, bool all)
320 return mv88e6xxx_g1_atu_flushmove(chip, fid, &entry, all);
323 static int mv88e6xxx_g1_atu_move(struct mv88e6xxx_chip *chip, u16 fid,
330 if (!chip->info->atu_move_port_mask)
333 mask = chip->info->atu_move_port_mask;
340 return mv88e6xxx_g1_atu_flushmove(chip, fid, &entry, all);
343 int mv88e6xxx_g1_atu_remove(struct mv88e6xxx_chip *chip, u16 fid, int port,
347 int to_port = chip->info->atu_move_port_mask;
349 return mv88e6xxx_g1_atu_move(chip, fid, from_port, to_port, all);
354 struct mv88e6xxx_chip *chip = dev_id;
360 mv88e6xxx_reg_lock(chip);
362 err = mv88e6xxx_g1_atu_op(chip, 0,
367 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_ATU_OP, &val);
371 err = mv88e6xxx_g1_atu_data_read(chip, &entry);
375 err = mv88e6xxx_g1_atu_mac_read(chip, &entry);
382 dev_err_ratelimited(chip->dev,
388 dev_err_ratelimited(chip->dev,
391 chip->ports[spid].atu_member_violation++;
395 dev_err_ratelimited(chip->dev,
398 chip->ports[spid].atu_miss_violation++;
402 dev_err_ratelimited(chip->dev,
405 chip->ports[spid].atu_full_violation++;
407 mv88e6xxx_reg_unlock(chip);
412 mv88e6xxx_reg_unlock(chip);
414 dev_err(chip->dev, "ATU problem: error %d while handling interrupt\n",
419 int mv88e6xxx_g1_atu_prob_irq_setup(struct mv88e6xxx_chip *chip)
423 chip->atu_prob_irq = irq_find_mapping(chip->g1_irq.domain,
425 if (chip->atu_prob_irq < 0)
426 return chip->atu_prob_irq;
428 snprintf(chip->atu_prob_irq_name, sizeof(chip->atu_prob_irq_name),
429 "mv88e6xxx-%s-g1-atu-prob", dev_name(chip->dev));
431 err = request_threaded_irq(chip->atu_prob_irq, NULL,
433 IRQF_ONESHOT, chip->atu_prob_irq_name,
434 chip);
436 irq_dispose_mapping(chip->atu_prob_irq);
441 void mv88e6xxx_g1_atu_prob_irq_free(struct mv88e6xxx_chip *chip)
443 free_irq(chip->atu_prob_irq, chip);
444 irq_dispose_mapping(chip->atu_prob_irq);