Lines Matching refs:chip
3 * Marvell 88e6xxx Ethernet switch single-chip support
34 #include "chip.h"
45 static void assert_reg_lock(struct mv88e6xxx_chip *chip)
47 if (unlikely(!mutex_is_locked(&chip->reg_lock))) {
48 dev_err(chip->dev, "Switch registers lock not held!\n");
53 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val)
57 assert_reg_lock(chip);
59 err = mv88e6xxx_smi_read(chip, addr, reg, val);
63 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
69 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val)
73 assert_reg_lock(chip);
75 err = mv88e6xxx_smi_write(chip, addr, reg, val);
79 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
85 int mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg,
94 err = mv88e6xxx_read(chip, addr, reg, &data);
104 dev_err(chip->dev, "Timeout while waiting for switch\n");
108 int mv88e6xxx_wait_bit(struct mv88e6xxx_chip *chip, int addr, int reg,
111 return mv88e6xxx_wait_mask(chip, addr, reg, BIT(bit),
115 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip)
119 mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus,
129 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
132 chip->g1_irq.masked |= (1 << n);
137 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
140 chip->g1_irq.masked &= ~(1 << n);
143 static irqreturn_t mv88e6xxx_g1_irq_thread_work(struct mv88e6xxx_chip *chip)
152 mv88e6xxx_reg_lock(chip);
153 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®);
154 mv88e6xxx_reg_unlock(chip);
160 for (n = 0; n < chip->g1_irq.nirqs; ++n) {
162 sub_irq = irq_find_mapping(chip->g1_irq.domain,
169 mv88e6xxx_reg_lock(chip);
170 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &ctl1);
173 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®);
175 mv88e6xxx_reg_unlock(chip);
178 ctl1 &= GENMASK(chip->g1_irq.nirqs, 0);
187 struct mv88e6xxx_chip *chip = dev_id;
189 return mv88e6xxx_g1_irq_thread_work(chip);
194 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
196 mv88e6xxx_reg_lock(chip);
201 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
202 u16 mask = GENMASK(chip->g1_irq.nirqs, 0);
206 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, ®);
211 reg |= (~chip->g1_irq.masked & mask);
213 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg);
218 mv88e6xxx_reg_unlock(chip);
233 struct mv88e6xxx_chip *chip = d->host_data;
236 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq);
248 static void mv88e6xxx_g1_irq_free_common(struct mv88e6xxx_chip *chip)
253 mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
254 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
255 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
257 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) {
258 virq = irq_find_mapping(chip->g1_irq.domain, irq);
262 irq_domain_remove(chip->g1_irq.domain);
265 static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip)
271 free_irq(chip->irq, chip);
273 mv88e6xxx_reg_lock(chip);
274 mv88e6xxx_g1_irq_free_common(chip);
275 mv88e6xxx_reg_unlock(chip);
278 static int mv88e6xxx_g1_irq_setup_common(struct mv88e6xxx_chip *chip)
283 chip->g1_irq.nirqs = chip->info->g1_irqs;
284 chip->g1_irq.domain = irq_domain_add_simple(
285 NULL, chip->g1_irq.nirqs, 0,
286 &mv88e6xxx_g1_irq_domain_ops, chip);
287 if (!chip->g1_irq.domain)
290 for (irq = 0; irq < chip->g1_irq.nirqs; irq++)
291 irq_create_mapping(chip->g1_irq.domain, irq);
293 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip;
294 chip->g1_irq.masked = ~0;
296 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
300 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
302 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
307 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®);
314 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
315 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
319 virq = irq_find_mapping(chip->g1_irq.domain, irq);
323 irq_domain_remove(chip->g1_irq.domain);
328 static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip)
334 err = mv88e6xxx_g1_irq_setup_common(chip);
342 irq_set_lockdep_class(chip->irq, &lock_key, &request_key);
344 snprintf(chip->irq_name, sizeof(chip->irq_name),
345 "mv88e6xxx-%s", dev_name(chip->dev));
347 mv88e6xxx_reg_unlock(chip);
348 err = request_threaded_irq(chip->irq, NULL,
351 chip->irq_name, chip);
352 mv88e6xxx_reg_lock(chip);
354 mv88e6xxx_g1_irq_free_common(chip);
361 struct mv88e6xxx_chip *chip = container_of(work,
364 mv88e6xxx_g1_irq_thread_work(chip);
366 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work,
370 static int mv88e6xxx_irq_poll_setup(struct mv88e6xxx_chip *chip)
374 err = mv88e6xxx_g1_irq_setup_common(chip);
378 kthread_init_delayed_work(&chip->irq_poll_work,
381 chip->kworker = kthread_create_worker(0, "%s", dev_name(chip->dev));
382 if (IS_ERR(chip->kworker))
383 return PTR_ERR(chip->kworker);
385 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work,
391 static void mv88e6xxx_irq_poll_free(struct mv88e6xxx_chip *chip)
393 kthread_cancel_delayed_work_sync(&chip->irq_poll_work);
394 kthread_destroy_worker(chip->kworker);
396 mv88e6xxx_reg_lock(chip);
397 mv88e6xxx_g1_irq_free_common(chip);
398 mv88e6xxx_reg_unlock(chip);
401 static int mv88e6xxx_port_config_interface(struct mv88e6xxx_chip *chip,
406 if (chip->info->ops->port_set_rgmii_delay) {
407 err = chip->info->ops->port_set_rgmii_delay(chip, port,
413 if (chip->info->ops->port_set_cmode) {
414 err = chip->info->ops->port_set_cmode(chip, port,
423 static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port,
429 if (!chip->info->ops->port_set_link)
433 err = chip->info->ops->port_set_link(chip, port, LINK_FORCED_DOWN);
437 if (chip->info->ops->port_set_speed_duplex) {
438 err = chip->info->ops->port_set_speed_duplex(chip, port,
444 if (speed == SPEED_MAX && chip->info->ops->port_max_speed_mode)
445 mode = chip->info->ops->port_max_speed_mode(port);
447 if (chip->info->ops->port_set_pause) {
448 err = chip->info->ops->port_set_pause(chip, port, pause);
453 err = mv88e6xxx_port_config_interface(chip, port, mode);
455 if (chip->info->ops->port_set_link(chip, port, link))
456 dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port);
463 struct mv88e6xxx_chip *chip = ds->priv;
465 return port < chip->info->num_internal_phys;
468 static int mv88e6xxx_port_ppu_updates(struct mv88e6xxx_chip *chip, int port)
473 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®);
475 dev_err(chip->dev,
487 struct mv88e6xxx_chip *chip = ds->priv;
491 mv88e6xxx_reg_lock(chip);
492 lane = mv88e6xxx_serdes_get_lane(chip, port);
493 if (lane && chip->info->ops->serdes_pcs_get_state)
494 err = chip->info->ops->serdes_pcs_get_state(chip, port, lane,
498 mv88e6xxx_reg_unlock(chip);
503 static int mv88e6xxx_serdes_pcs_config(struct mv88e6xxx_chip *chip, int port,
508 const struct mv88e6xxx_ops *ops = chip->info->ops;
512 lane = mv88e6xxx_serdes_get_lane(chip, port);
514 return ops->serdes_pcs_config(chip, port, lane, mode,
523 struct mv88e6xxx_chip *chip = ds->priv;
528 ops = chip->info->ops;
531 mv88e6xxx_reg_lock(chip);
532 lane = mv88e6xxx_serdes_get_lane(chip, port);
534 err = ops->serdes_pcs_an_restart(chip, port, lane);
535 mv88e6xxx_reg_unlock(chip);
542 static int mv88e6xxx_serdes_pcs_link_up(struct mv88e6xxx_chip *chip, int port,
546 const struct mv88e6xxx_ops *ops = chip->info->ops;
550 lane = mv88e6xxx_serdes_get_lane(chip, port);
552 return ops->serdes_pcs_link_up(chip, port, lane,
559 static void mv88e6065_phylink_validate(struct mv88e6xxx_chip *chip, int port,
572 static void mv88e6185_phylink_validate(struct mv88e6xxx_chip *chip, int port,
582 mv88e6065_phylink_validate(chip, port, mask, state);
585 static void mv88e6341_phylink_validate(struct mv88e6xxx_chip *chip, int port,
596 mv88e6065_phylink_validate(chip, port, mask, state);
599 static void mv88e6352_phylink_validate(struct mv88e6xxx_chip *chip, int port,
607 mv88e6065_phylink_validate(chip, port, mask, state);
610 static void mv88e6390_phylink_validate(struct mv88e6xxx_chip *chip, int port,
623 mv88e6065_phylink_validate(chip, port, mask, state);
626 static void mv88e6390x_phylink_validate(struct mv88e6xxx_chip *chip, int port,
635 mv88e6390_phylink_validate(chip, port, mask, state);
643 struct mv88e6xxx_chip *chip = ds->priv;
650 if (chip->info->ops->phylink_validate)
651 chip->info->ops->phylink_validate(chip, port, mask, state);
667 struct mv88e6xxx_chip *chip = ds->priv;
671 p = &chip->ports[port];
673 mv88e6xxx_reg_lock(chip);
682 chip->info->ops->port_set_link)
683 chip->info->ops->port_set_link(chip, port,
686 err = mv88e6xxx_port_config_interface(chip, port,
691 err = mv88e6xxx_serdes_pcs_config(chip, port, mode,
708 if (chip->info->ops->port_set_link &&
710 (mode == MLO_AN_PHY && mv88e6xxx_port_ppu_updates(chip, port))))
711 chip->info->ops->port_set_link(chip, port, LINK_UNFORCED);
716 mv88e6xxx_reg_unlock(chip);
726 struct mv88e6xxx_chip *chip = ds->priv;
730 ops = chip->info->ops;
732 mv88e6xxx_reg_lock(chip);
737 !mv88e6xxx_port_ppu_updates(chip, port)) ||
739 err = ops->port_set_link(chip, port, LINK_FORCED_DOWN);
740 mv88e6xxx_reg_unlock(chip);
743 dev_err(chip->dev,
753 struct mv88e6xxx_chip *chip = ds->priv;
757 ops = chip->info->ops;
759 mv88e6xxx_reg_lock(chip);
764 !mv88e6xxx_port_ppu_updates(chip, port)) ||
772 err = mv88e6xxx_serdes_pcs_link_up(chip, port, mode, speed,
778 err = ops->port_set_speed_duplex(chip, port,
785 err = ops->port_set_link(chip, port, LINK_FORCED_UP);
788 mv88e6xxx_reg_unlock(chip);
795 static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
797 if (!chip->info->ops->stats_snapshot)
800 return chip->info->ops->stats_snapshot(chip, port);
865 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip,
878 err = mv88e6xxx_port_read(chip, port, s->reg, ®);
884 err = mv88e6xxx_port_read(chip, port, s->reg + 1, ®);
895 mv88e6xxx_g1_stats_read(chip, reg, &low);
897 mv88e6xxx_g1_stats_read(chip, reg + 1, &high);
906 static int mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip,
924 static int mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip,
927 return mv88e6xxx_stats_get_strings(chip, data,
931 static int mv88e6250_stats_get_strings(struct mv88e6xxx_chip *chip,
934 return mv88e6xxx_stats_get_strings(chip, data, STATS_TYPE_BANK0);
937 static int mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip,
940 return mv88e6xxx_stats_get_strings(chip, data,
965 struct mv88e6xxx_chip *chip = ds->priv;
971 mv88e6xxx_reg_lock(chip);
973 if (chip->info->ops->stats_get_strings)
974 count = chip->info->ops->stats_get_strings(chip, data);
976 if (chip->info->ops->serdes_get_strings) {
978 count = chip->info->ops->serdes_get_strings(chip, port, data);
984 mv88e6xxx_reg_unlock(chip);
987 static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip,
1001 static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip)
1003 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
1007 static int mv88e6250_stats_get_sset_count(struct mv88e6xxx_chip *chip)
1009 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0);
1012 static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip)
1014 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
1020 struct mv88e6xxx_chip *chip = ds->priv;
1027 mv88e6xxx_reg_lock(chip);
1028 if (chip->info->ops->stats_get_sset_count)
1029 count = chip->info->ops->stats_get_sset_count(chip);
1033 if (chip->info->ops->serdes_get_sset_count)
1034 serdes_count = chip->info->ops->serdes_get_sset_count(chip,
1044 mv88e6xxx_reg_unlock(chip);
1049 static int mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1059 mv88e6xxx_reg_lock(chip);
1060 data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port,
1063 mv88e6xxx_reg_unlock(chip);
1071 static int mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1074 return mv88e6xxx_stats_get_stats(chip, port, data,
1079 static int mv88e6250_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1082 return mv88e6xxx_stats_get_stats(chip, port, data, STATS_TYPE_BANK0,
1086 static int mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1089 return mv88e6xxx_stats_get_stats(chip, port, data,
1095 static int mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1098 return mv88e6xxx_stats_get_stats(chip, port, data,
1104 static void mv88e6xxx_atu_vtu_get_stats(struct mv88e6xxx_chip *chip, int port,
1107 *data++ = chip->ports[port].atu_member_violation;
1108 *data++ = chip->ports[port].atu_miss_violation;
1109 *data++ = chip->ports[port].atu_full_violation;
1110 *data++ = chip->ports[port].vtu_member_violation;
1111 *data++ = chip->ports[port].vtu_miss_violation;
1114 static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port,
1119 if (chip->info->ops->stats_get_stats)
1120 count = chip->info->ops->stats_get_stats(chip, port, data);
1122 mv88e6xxx_reg_lock(chip);
1123 if (chip->info->ops->serdes_get_stats) {
1125 count = chip->info->ops->serdes_get_stats(chip, port, data);
1128 mv88e6xxx_atu_vtu_get_stats(chip, port, data);
1129 mv88e6xxx_reg_unlock(chip);
1135 struct mv88e6xxx_chip *chip = ds->priv;
1138 mv88e6xxx_reg_lock(chip);
1140 ret = mv88e6xxx_stats_snapshot(chip, port);
1141 mv88e6xxx_reg_unlock(chip);
1146 mv88e6xxx_get_stats(chip, port, data);
1152 struct mv88e6xxx_chip *chip = ds->priv;
1156 if (chip->info->ops->serdes_get_regs_len)
1157 len += chip->info->ops->serdes_get_regs_len(chip, port);
1165 struct mv88e6xxx_chip *chip = ds->priv;
1171 regs->version = chip->info->prod_num;
1175 mv88e6xxx_reg_lock(chip);
1179 err = mv88e6xxx_port_read(chip, port, i, ®);
1184 if (chip->info->ops->serdes_get_regs)
1185 chip->info->ops->serdes_get_regs(chip, port, &p[i]);
1187 mv88e6xxx_reg_unlock(chip);
1205 static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port)
1207 struct dsa_switch *ds = chip->ds;
1227 return mv88e6xxx_port_mask(chip);
1245 static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port)
1247 u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port);
1252 return mv88e6xxx_port_set_vlan_map(chip, port, output_ports);
1258 struct mv88e6xxx_chip *chip = ds->priv;
1261 mv88e6xxx_reg_lock(chip);
1262 err = mv88e6xxx_port_set_state(chip, port, state);
1263 mv88e6xxx_reg_unlock(chip);
1269 static int mv88e6xxx_pri_setup(struct mv88e6xxx_chip *chip)
1273 if (chip->info->ops->ieee_pri_map) {
1274 err = chip->info->ops->ieee_pri_map(chip);
1279 if (chip->info->ops->ip_pri_map) {
1280 err = chip->info->ops->ip_pri_map(chip);
1288 static int mv88e6xxx_devmap_setup(struct mv88e6xxx_chip *chip)
1290 struct dsa_switch *ds = chip->ds;
1294 if (!chip->info->global2_addr)
1303 err = mv88e6xxx_g2_device_mapping_write(chip, target, port);
1308 if (chip->info->ops->set_cascade_port) {
1310 err = chip->info->ops->set_cascade_port(chip, port);
1315 err = mv88e6xxx_g1_set_device_number(chip, chip->ds->index);
1322 static int mv88e6xxx_trunk_setup(struct mv88e6xxx_chip *chip)
1325 if (chip->info->global2_addr)
1326 return mv88e6xxx_g2_trunk_clear(chip);
1331 static int mv88e6xxx_rmu_setup(struct mv88e6xxx_chip *chip)
1333 if (chip->info->ops->rmu_disable)
1334 return chip->info->ops->rmu_disable(chip);
1339 static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip)
1341 if (chip->info->ops->pot_clear)
1342 return chip->info->ops->pot_clear(chip);
1347 static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip *chip)
1349 if (chip->info->ops->mgmt_rsvd2cpu)
1350 return chip->info->ops->mgmt_rsvd2cpu(chip);
1355 static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip)
1359 err = mv88e6xxx_g1_atu_flush(chip, 0, true);
1363 err = mv88e6xxx_g1_atu_set_learn2all(chip, true);
1367 return mv88e6xxx_g1_atu_set_age_time(chip, 300000);
1370 static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip)
1375 if (!chip->info->ops->irl_init_all)
1378 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
1382 err = chip->info->ops->irl_init_all(chip, port);
1390 static int mv88e6xxx_mac_setup(struct mv88e6xxx_chip *chip)
1392 if (chip->info->ops->set_switch_mac) {
1397 return chip->info->ops->set_switch_mac(chip, addr);
1403 static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port)
1407 if (!mv88e6xxx_has_pvt(chip))
1410 /* Skip the local source device, which uses in-chip port VLAN */
1411 if (dev != chip->ds->index)
1412 pvlan = mv88e6xxx_port_vlan(chip, dev, port);
1414 return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan);
1417 static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip)
1422 if (!mv88e6xxx_has_pvt(chip))
1428 err = mv88e6xxx_g2_misc_4_bit_port(chip);
1434 err = mv88e6xxx_pvt_map(chip, dev, port);
1445 struct mv88e6xxx_chip *chip = ds->priv;
1448 mv88e6xxx_reg_lock(chip);
1449 err = mv88e6xxx_g1_atu_remove(chip, 0, port, false);
1450 mv88e6xxx_reg_unlock(chip);
1456 static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip)
1458 if (!chip->info->max_vid)
1461 return mv88e6xxx_g1_vtu_flush(chip);
1464 static int mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip *chip,
1467 if (!chip->info->ops->vtu_getnext)
1470 return chip->info->ops->vtu_getnext(chip, entry);
1473 static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip,
1476 if (!chip->info->ops->vtu_loadpurge)
1479 return chip->info->ops->vtu_loadpurge(chip, entry);
1482 int mv88e6xxx_fid_map(struct mv88e6xxx_chip *chip, unsigned long *fid_bitmap)
1491 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1492 err = mv88e6xxx_port_get_fid(chip, i, &fid);
1500 vlan.vid = chip->info->max_vid;
1504 err = mv88e6xxx_vtu_getnext(chip, &vlan);
1512 } while (vlan.vid < chip->info->max_vid);
1517 static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid)
1522 err = mv88e6xxx_fid_map(chip, fid_bitmap);
1530 if (unlikely(*fid >= mv88e6xxx_num_databases(chip)))
1534 return mv88e6xxx_g1_atu_flush(chip, *fid, true);
1540 struct mv88e6xxx_chip *chip = ds->priv;
1555 err = mv88e6xxx_vtu_getnext(chip, &vlan);
1565 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1597 struct mv88e6xxx_chip *chip = ds->priv;
1603 return chip->info->max_vid ? 0 : -EOPNOTSUPP;
1605 mv88e6xxx_reg_lock(chip);
1606 err = mv88e6xxx_port_set_8021q_mode(chip, port, mode);
1607 mv88e6xxx_reg_unlock(chip);
1616 struct mv88e6xxx_chip *chip = ds->priv;
1619 if (!chip->info->max_vid)
1625 mv88e6xxx_reg_lock(chip);
1628 mv88e6xxx_reg_unlock(chip);
1636 static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port,
1647 err = mv88e6xxx_port_get_fid(chip, port, &fid);
1654 err = mv88e6xxx_vtu_getnext(chip, &vlan);
1669 err = mv88e6xxx_g1_atu_getnext(chip, fid, &entry);
1693 return mv88e6xxx_g1_atu_loadpurge(chip, fid, &entry);
1696 static int mv88e6xxx_policy_apply(struct mv88e6xxx_chip *chip, int port,
1707 if (!chip->info->ops->port_set_policy)
1724 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid,
1735 idr_for_each_entry(&chip->policies, policy, id)
1741 return chip->info->ops->port_set_policy(chip, port, mapping, action);
1744 static int mv88e6xxx_policy_insert(struct mv88e6xxx_chip *chip, int port,
1790 idr_for_each_entry(&chip->policies, policy, id) {
1797 policy = devm_kzalloc(chip->dev, sizeof(*policy), GFP_KERNEL);
1802 err = idr_alloc_u32(&chip->policies, policy, &fs->location, 0xffffffff,
1805 devm_kfree(chip->dev, policy);
1816 err = mv88e6xxx_policy_apply(chip, port, policy);
1818 idr_remove(&chip->policies, fs->location);
1819 devm_kfree(chip->dev, policy);
1830 struct mv88e6xxx_chip *chip = ds->priv;
1835 mv88e6xxx_reg_lock(chip);
1842 idr_for_each_entry(&chip->policies, policy, id)
1849 policy = idr_find(&chip->policies, fs->location);
1858 idr_for_each_entry(&chip->policies, policy, id)
1868 mv88e6xxx_reg_unlock(chip);
1877 struct mv88e6xxx_chip *chip = ds->priv;
1881 mv88e6xxx_reg_lock(chip);
1885 err = mv88e6xxx_policy_insert(chip, port, fs);
1889 policy = idr_remove(&chip->policies, fs->location);
1892 err = mv88e6xxx_policy_apply(chip, port, policy);
1893 devm_kfree(chip->dev, policy);
1901 mv88e6xxx_reg_unlock(chip);
1906 static int mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip *chip, int port,
1912 return mv88e6xxx_port_db_load_purge(chip, port, broadcast, vid, state);
1915 static int mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip *chip, u16 vid)
1920 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
1921 err = mv88e6xxx_port_add_broadcast(chip, port, vid);
1929 static int mv88e6xxx_port_vlan_join(struct mv88e6xxx_chip *chip, int port,
1942 err = mv88e6xxx_vtu_getnext(chip, &vlan);
1949 err = mv88e6xxx_atu_new(chip, &vlan.fid);
1953 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
1962 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
1966 err = mv88e6xxx_broadcast_setup(chip, vlan.vid);
1972 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
1976 dev_info(chip->dev, "p%d: already a member of VLAN %d\n",
1986 struct mv88e6xxx_chip *chip = ds->priv;
1993 if (!chip->info->max_vid)
2008 mv88e6xxx_reg_lock(chip);
2011 if (mv88e6xxx_port_vlan_join(chip, port, vid, member, warn))
2015 if (pvid && mv88e6xxx_port_set_pvid(chip, port, vlan->vid_end))
2019 mv88e6xxx_reg_unlock(chip);
2022 static int mv88e6xxx_port_vlan_leave(struct mv88e6xxx_chip *chip,
2034 err = mv88e6xxx_vtu_getnext(chip, &vlan);
2049 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
2057 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
2061 return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false);
2067 struct mv88e6xxx_chip *chip = ds->priv;
2071 if (!chip->info->max_vid)
2074 mv88e6xxx_reg_lock(chip);
2076 err = mv88e6xxx_port_get_pvid(chip, port, &pvid);
2081 err = mv88e6xxx_port_vlan_leave(chip, port, vid);
2086 err = mv88e6xxx_port_set_pvid(chip, port, 0);
2093 mv88e6xxx_reg_unlock(chip);
2101 struct mv88e6xxx_chip *chip = ds->priv;
2104 mv88e6xxx_reg_lock(chip);
2105 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid,
2107 mv88e6xxx_reg_unlock(chip);
2115 struct mv88e6xxx_chip *chip = ds->priv;
2118 mv88e6xxx_reg_lock(chip);
2119 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 0);
2120 mv88e6xxx_reg_unlock(chip);
2125 static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip,
2137 err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr);
2160 static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port,
2168 err = mv88e6xxx_port_get_fid(chip, port, &fid);
2172 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, cb, data);
2177 vlan.vid = chip->info->max_vid;
2181 err = mv88e6xxx_vtu_getnext(chip, &vlan);
2188 err = mv88e6xxx_port_db_dump_fid(chip, vlan.fid, vlan.vid, port,
2192 } while (vlan.vid < chip->info->max_vid);
2200 struct mv88e6xxx_chip *chip = ds->priv;
2203 mv88e6xxx_reg_lock(chip);
2204 err = mv88e6xxx_port_db_dump(chip, port, cb, data);
2205 mv88e6xxx_reg_unlock(chip);
2210 static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip,
2213 struct dsa_switch *ds = chip->ds;
2224 err = mv88e6xxx_port_vlan_map(chip, dp->index);
2229 * remap its cross-chip Port VLAN Table entry.
2231 err = mv88e6xxx_pvt_map(chip, dp->ds->index,
2245 struct mv88e6xxx_chip *chip = ds->priv;
2248 mv88e6xxx_reg_lock(chip);
2249 err = mv88e6xxx_bridge_map(chip, br);
2250 mv88e6xxx_reg_unlock(chip);
2258 struct mv88e6xxx_chip *chip = ds->priv;
2260 mv88e6xxx_reg_lock(chip);
2261 if (mv88e6xxx_bridge_map(chip, br) ||
2262 mv88e6xxx_port_vlan_map(chip, port))
2263 dev_err(ds->dev, "failed to remap in-chip Port VLAN\n");
2264 mv88e6xxx_reg_unlock(chip);
2271 struct mv88e6xxx_chip *chip = ds->priv;
2277 mv88e6xxx_reg_lock(chip);
2278 err = mv88e6xxx_pvt_map(chip, sw_index, port);
2279 mv88e6xxx_reg_unlock(chip);
2288 struct mv88e6xxx_chip *chip = ds->priv;
2293 mv88e6xxx_reg_lock(chip);
2294 if (mv88e6xxx_pvt_map(chip, sw_index, port))
2295 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n");
2296 mv88e6xxx_reg_unlock(chip);
2299 static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip)
2301 if (chip->info->ops->reset)
2302 return chip->info->ops->reset(chip);
2307 static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip)
2309 struct gpio_desc *gpiod = chip->reset;
2319 if (chip->info->ops->get_eeprom)
2320 mv88e6xxx_g2_eeprom_wait(chip);
2327 if (chip->info->ops->get_eeprom)
2328 mv88e6xxx_g2_eeprom_wait(chip);
2332 static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip)
2337 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
2338 err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED);
2351 static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip)
2355 err = mv88e6xxx_disable_ports(chip);
2359 mv88e6xxx_hardware_reset(chip);
2361 return mv88e6xxx_software_reset(chip);
2364 static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port,
2370 if (!chip->info->ops->port_set_frame_mode)
2373 err = mv88e6xxx_port_set_egress_mode(chip, port, egress);
2377 err = chip->info->ops->port_set_frame_mode(chip, port, frame);
2381 if (chip->info->ops->port_set_ether_type)
2382 return chip->info->ops->port_set_ether_type(chip, port, etype);
2387 static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port)
2389 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL,
2394 static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port)
2396 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA,
2401 static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port)
2403 return mv88e6xxx_set_port_mode(chip, port,
2409 static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port)
2411 if (dsa_is_dsa_port(chip->ds, port))
2412 return mv88e6xxx_set_port_mode_dsa(chip, port);
2414 if (dsa_is_user_port(chip->ds, port))
2415 return mv88e6xxx_set_port_mode_normal(chip, port);
2418 if (chip->info->tag_protocol == DSA_TAG_PROTO_DSA)
2419 return mv88e6xxx_set_port_mode_dsa(chip, port);
2421 if (chip->info->tag_protocol == DSA_TAG_PROTO_EDSA)
2422 return mv88e6xxx_set_port_mode_edsa(chip, port);
2427 static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port)
2429 bool message = dsa_is_dsa_port(chip->ds, port);
2431 return mv88e6xxx_port_set_message_port(chip, port, message);
2434 static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port)
2436 struct dsa_switch *ds = chip->ds;
2441 if (chip->info->ops->port_set_egress_floods)
2442 return chip->info->ops->port_set_egress_floods(chip, port,
2451 struct mv88e6xxx_chip *chip = mvp->chip;
2456 mv88e6xxx_reg_lock(chip);
2457 lane = mv88e6xxx_serdes_get_lane(chip, port);
2459 ret = mv88e6xxx_serdes_irq_status(chip, port, lane);
2460 mv88e6xxx_reg_unlock(chip);
2465 static int mv88e6xxx_serdes_irq_request(struct mv88e6xxx_chip *chip, int port,
2468 struct mv88e6xxx_port *dev_id = &chip->ports[port];
2473 irq = mv88e6xxx_serdes_irq_mapping(chip, port);
2478 "mv88e6xxx-%s-serdes-%d", dev_name(chip->dev), port);
2481 mv88e6xxx_reg_unlock(chip);
2485 mv88e6xxx_reg_lock(chip);
2491 return mv88e6xxx_serdes_irq_enable(chip, port, lane);
2494 static int mv88e6xxx_serdes_irq_free(struct mv88e6xxx_chip *chip, int port,
2497 struct mv88e6xxx_port *dev_id = &chip->ports[port];
2505 err = mv88e6xxx_serdes_irq_disable(chip, port, lane);
2508 mv88e6xxx_reg_unlock(chip);
2510 mv88e6xxx_reg_lock(chip);
2517 static int mv88e6xxx_serdes_power(struct mv88e6xxx_chip *chip, int port,
2523 lane = mv88e6xxx_serdes_get_lane(chip, port);
2528 err = mv88e6xxx_serdes_power_up(chip, port, lane);
2532 err = mv88e6xxx_serdes_irq_request(chip, port, lane);
2534 err = mv88e6xxx_serdes_irq_free(chip, port, lane);
2538 err = mv88e6xxx_serdes_power_down(chip, port, lane);
2544 static int mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip *chip, int port)
2546 struct dsa_switch *ds = chip->ds;
2551 if (chip->info->ops->port_set_upstream_port) {
2552 err = chip->info->ops->port_set_upstream_port(chip, port,
2559 if (chip->info->ops->set_cpu_port) {
2560 err = chip->info->ops->set_cpu_port(chip,
2566 if (chip->info->ops->set_egress_port) {
2567 err = chip->info->ops->set_egress_port(chip,
2573 err = chip->info->ops->set_egress_port(chip,
2584 static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port)
2586 struct dsa_switch *ds = chip->ds;
2590 chip->ports[port].chip = chip;
2591 chip->ports[port].port = port;
2598 err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP,
2603 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED,
2632 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
2636 err = mv88e6xxx_setup_port_mode(chip, port);
2640 err = mv88e6xxx_setup_egress_floods(chip, port);
2650 err = mv88e6xxx_port_set_map_da(chip, port);
2654 err = mv88e6xxx_setup_upstream_port(chip, port);
2658 err = mv88e6xxx_port_set_8021q_mode(chip, port,
2663 if (chip->info->ops->port_set_jumbo_size) {
2664 err = chip->info->ops->port_set_jumbo_size(chip, port, 10218);
2679 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR,
2685 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2,
2690 if (chip->info->ops->port_pause_limit) {
2691 err = chip->info->ops->port_pause_limit(chip, port, 0, 0);
2696 if (chip->info->ops->port_disable_learn_limit) {
2697 err = chip->info->ops->port_disable_learn_limit(chip, port);
2702 if (chip->info->ops->port_disable_pri_override) {
2703 err = chip->info->ops->port_disable_pri_override(chip, port);
2708 if (chip->info->ops->port_tag_remap) {
2709 err = chip->info->ops->port_tag_remap(chip, port);
2714 if (chip->info->ops->port_egress_rate_limiting) {
2715 err = chip->info->ops->port_egress_rate_limiting(chip, port);
2720 if (chip->info->ops->port_setup_message_port) {
2721 err = chip->info->ops->port_setup_message_port(chip, port);
2730 err = mv88e6xxx_port_set_fid(chip, port, 0);
2734 err = mv88e6xxx_port_vlan_map(chip, port);
2741 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0);
2746 struct mv88e6xxx_chip *chip = ds->priv;
2748 if (chip->info->ops->port_set_jumbo_size)
2750 else if (chip->info->ops->set_max_frame_size)
2757 struct mv88e6xxx_chip *chip = ds->priv;
2763 if (!chip->info->ops->port_set_jumbo_size &&
2764 !chip->info->ops->set_max_frame_size) {
2774 mv88e6xxx_reg_lock(chip);
2775 if (chip->info->ops->port_set_jumbo_size)
2776 ret = chip->info->ops->port_set_jumbo_size(chip, port, new_mtu);
2777 else if (chip->info->ops->set_max_frame_size)
2778 ret = chip->info->ops->set_max_frame_size(chip, new_mtu);
2779 mv88e6xxx_reg_unlock(chip);
2787 struct mv88e6xxx_chip *chip = ds->priv;
2790 mv88e6xxx_reg_lock(chip);
2791 err = mv88e6xxx_serdes_power(chip, port, true);
2792 mv88e6xxx_reg_unlock(chip);
2799 struct mv88e6xxx_chip *chip = ds->priv;
2801 mv88e6xxx_reg_lock(chip);
2802 if (mv88e6xxx_serdes_power(chip, port, false))
2803 dev_err(chip->dev, "failed to power off SERDES\n");
2804 mv88e6xxx_reg_unlock(chip);
2810 struct mv88e6xxx_chip *chip = ds->priv;
2813 mv88e6xxx_reg_lock(chip);
2814 err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time);
2815 mv88e6xxx_reg_unlock(chip);
2820 static int mv88e6xxx_stats_setup(struct mv88e6xxx_chip *chip)
2825 if (chip->info->ops->stats_set_histogram) {
2826 err = chip->info->ops->stats_set_histogram(chip);
2831 return mv88e6xxx_g1_stats_clear(chip);
2835 static bool mv88e6390_setup_errata_applied(struct mv88e6xxx_chip *chip)
2841 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
2842 err = mv88e6xxx_port_hidden_read(chip, 0xf, port, 0, &val);
2844 dev_err(chip->dev,
2859 static int mv88e6390_setup_errata(struct mv88e6xxx_chip *chip)
2864 if (mv88e6390_setup_errata_applied(chip))
2868 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
2869 err = mv88e6xxx_port_set_state(chip, port, BR_STATE_DISABLED);
2874 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
2875 err = mv88e6xxx_port_hidden_write(chip, 0xf, port, 0, 0x01c0);
2880 return mv88e6xxx_software_reset(chip);
2892 struct mv88e6xxx_chip *chip = ds->priv;
2897 chip->ds = ds;
2898 ds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip);
2900 mv88e6xxx_reg_lock(chip);
2902 if (chip->info->ops->setup_errata) {
2903 err = chip->info->ops->setup_errata(chip);
2909 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
2910 if (chip->info->ops->port_get_cmode) {
2911 err = chip->info->ops->port_get_cmode(chip, i, &cmode);
2915 chip->ports[i].cmode = cmode;
2920 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
2925 if (mv88e6xxx_is_invalid_port(chip, i)) {
2926 dev_err(chip->dev, "port %d is invalid\n", i);
2931 err = mv88e6xxx_setup_port(chip, i);
2936 err = mv88e6xxx_irl_setup(chip);
2940 err = mv88e6xxx_mac_setup(chip);
2944 err = mv88e6xxx_phy_setup(chip);
2948 err = mv88e6xxx_vtu_setup(chip);
2952 err = mv88e6xxx_pvt_setup(chip);
2956 err = mv88e6xxx_atu_setup(chip);
2960 err = mv88e6xxx_broadcast_setup(chip, 0);
2964 err = mv88e6xxx_pot_setup(chip);
2968 err = mv88e6xxx_rmu_setup(chip);
2972 err = mv88e6xxx_rsvd2cpu_setup(chip);
2976 err = mv88e6xxx_trunk_setup(chip);
2980 err = mv88e6xxx_devmap_setup(chip);
2984 err = mv88e6xxx_pri_setup(chip);
2989 if (chip->info->ptp_support) {
2990 err = mv88e6xxx_ptp_setup(chip);
2994 err = mv88e6xxx_hwtstamp_setup(chip);
2999 err = mv88e6xxx_stats_setup(chip);
3004 mv88e6xxx_reg_unlock(chip);
3045 struct mv88e6xxx_chip *chip = mdio_bus->chip;
3050 if (!chip->info->ops->phy_read)
3053 mv88e6xxx_reg_lock(chip);
3054 err = chip->info->ops->phy_read(chip, bus, phy, reg, &val);
3055 mv88e6xxx_reg_unlock(chip);
3059 chip->info->family < ARRAY_SIZE(family_prod_id_table)) {
3060 prod_id = family_prod_id_table[chip->info->family];
3071 struct mv88e6xxx_chip *chip = mdio_bus->chip;
3074 if (!chip->info->ops->phy_write)
3077 mv88e6xxx_reg_lock(chip);
3078 err = chip->info->ops->phy_write(chip, bus, phy, reg, val);
3079 mv88e6xxx_reg_unlock(chip);
3084 static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip,
3094 mv88e6xxx_reg_lock(chip);
3095 err = mv88e6xxx_g2_scratch_gpio_set_smi(chip, true);
3096 mv88e6xxx_reg_unlock(chip);
3108 mdio_bus->chip = chip;
3122 bus->parent = chip->dev;
3125 err = mv88e6xxx_g2_irq_mdio_setup(chip, bus);
3132 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err);
3133 mv88e6xxx_g2_irq_mdio_free(chip, bus);
3138 list_add_tail(&mdio_bus->list, &chip->mdios);
3140 list_add(&mdio_bus->list, &chip->mdios);
3149 static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip)
3155 list_for_each_entry(mdio_bus, &chip->mdios, list) {
3159 mv88e6xxx_g2_irq_mdio_free(chip, bus);
3166 static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip,
3177 err = mv88e6xxx_mdio_register(chip, child, false);
3189 err = mv88e6xxx_mdio_register(chip, child, true);
3191 mv88e6xxx_mdios_unregister(chip);
3203 struct mv88e6xxx_chip *chip = ds->priv;
3205 return chip->eeprom_len;
3211 struct mv88e6xxx_chip *chip = ds->priv;
3214 if (!chip->info->ops->get_eeprom)
3217 mv88e6xxx_reg_lock(chip);
3218 err = chip->info->ops->get_eeprom(chip, eeprom, data);
3219 mv88e6xxx_reg_unlock(chip);
3232 struct mv88e6xxx_chip *chip = ds->priv;
3235 if (!chip->info->ops->set_eeprom)
3241 mv88e6xxx_reg_lock(chip);
3242 err = chip->info->ops->set_eeprom(chip, eeprom, data);
3243 mv88e6xxx_reg_unlock(chip);
5211 static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip)
5218 mv88e6xxx_reg_lock(chip);
5219 err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id);
5220 mv88e6xxx_reg_unlock(chip);
5232 chip->info = info;
5234 err = mv88e6xxx_g2_require(chip);
5238 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n",
5239 chip->info->prod_num, chip->info->name, rev);
5246 struct mv88e6xxx_chip *chip;
5248 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
5249 if (!chip)
5252 chip->dev = dev;
5254 mutex_init(&chip->reg_lock);
5255 INIT_LIST_HEAD(&chip->mdios);
5256 idr_init(&chip->policies);
5258 return chip;
5265 struct mv88e6xxx_chip *chip = ds->priv;
5267 return chip->info->tag_protocol;
5283 struct mv88e6xxx_chip *chip = ds->priv;
5285 mv88e6xxx_reg_lock(chip);
5286 if (mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
5290 mv88e6xxx_reg_unlock(chip);
5296 struct mv88e6xxx_chip *chip = ds->priv;
5299 mv88e6xxx_reg_lock(chip);
5300 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 0);
5301 mv88e6xxx_reg_unlock(chip);
5313 struct mv88e6xxx_chip *chip = ds->priv;
5318 if (!chip->info->ops->set_egress_port)
5321 mutex_lock(&chip->reg_lock);
5322 if ((ingress ? chip->ingress_dest_port : chip->egress_dest_port) !=
5324 for (i = 0; i < mv88e6xxx_num_ports(chip); i++)
5326 chip->ports[i].mirror_ingress :
5327 chip->ports[i].mirror_egress;
5335 err = chip->info->ops->set_egress_port(chip,
5342 err = mv88e6xxx_port_set_mirror(chip, port, direction, true);
5344 mutex_unlock(&chip->reg_lock);
5355 struct mv88e6xxx_chip *chip = ds->priv;
5359 mutex_lock(&chip->reg_lock);
5360 if (mv88e6xxx_port_set_mirror(chip, port, direction, false))
5363 for (i = 0; i < mv88e6xxx_num_ports(chip); i++)
5365 chip->ports[i].mirror_ingress :
5366 chip->ports[i].mirror_egress;
5370 if (chip->info->ops->set_egress_port(chip,
5377 mutex_unlock(&chip->reg_lock);
5383 struct mv88e6xxx_chip *chip = ds->priv;
5386 mv88e6xxx_reg_lock(chip);
5387 if (chip->info->ops->port_set_egress_floods)
5388 err = chip->info->ops->port_set_egress_floods(chip, port,
5391 mv88e6xxx_reg_unlock(chip);
5452 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip)
5454 struct device *dev = chip->dev;
5462 ds->num_ports = mv88e6xxx_num_ports(chip);
5463 ds->priv = chip;
5466 ds->ageing_time_min = chip->info->age_time_coeff;
5467 ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX;
5474 static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip)
5476 dsa_unregister_switch(chip->ds);
5513 struct mv88e6xxx_chip *chip;
5542 chip = mv88e6xxx_alloc_chip(dev);
5543 if (!chip) {
5548 chip->info = compat_info;
5550 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr);
5554 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
5555 if (IS_ERR(chip->reset)) {
5556 err = PTR_ERR(chip->reset);
5559 if (chip->reset)
5562 err = mv88e6xxx_detect(chip);
5566 mv88e6xxx_phy_init(chip);
5568 if (chip->info->ops->get_eeprom) {
5571 &chip->eeprom_len);
5573 chip->eeprom_len = pdata->eeprom_len;
5576 mv88e6xxx_reg_lock(chip);
5577 err = mv88e6xxx_switch_reset(chip);
5578 mv88e6xxx_reg_unlock(chip);
5583 chip->irq = of_irq_get(np, 0);
5584 if (chip->irq == -EPROBE_DEFER) {
5585 err = chip->irq;
5591 chip->irq = pdata->irq;
5597 mv88e6xxx_reg_lock(chip);
5598 if (chip->irq > 0)
5599 err = mv88e6xxx_g1_irq_setup(chip);
5601 err = mv88e6xxx_irq_poll_setup(chip);
5602 mv88e6xxx_reg_unlock(chip);
5607 if (chip->info->g2_irqs > 0) {
5608 err = mv88e6xxx_g2_irq_setup(chip);
5613 err = mv88e6xxx_g1_atu_prob_irq_setup(chip);
5617 err = mv88e6xxx_g1_vtu_prob_irq_setup(chip);
5621 err = mv88e6xxx_mdios_register(chip, np);
5625 err = mv88e6xxx_register_switch(chip);
5632 mv88e6xxx_mdios_unregister(chip);
5634 mv88e6xxx_g1_vtu_prob_irq_free(chip);
5636 mv88e6xxx_g1_atu_prob_irq_free(chip);
5638 if (chip->info->g2_irqs > 0)
5639 mv88e6xxx_g2_irq_free(chip);
5641 if (chip->irq > 0)
5642 mv88e6xxx_g1_irq_free(chip);
5644 mv88e6xxx_irq_poll_free(chip);
5655 struct mv88e6xxx_chip *chip = ds->priv;
5657 if (chip->info->ptp_support) {
5658 mv88e6xxx_hwtstamp_free(chip);
5659 mv88e6xxx_ptp_free(chip);
5662 mv88e6xxx_phy_destroy(chip);
5663 mv88e6xxx_unregister_switch(chip);
5664 mv88e6xxx_mdios_unregister(chip);
5666 mv88e6xxx_g1_vtu_prob_irq_free(chip);
5667 mv88e6xxx_g1_atu_prob_irq_free(chip);
5669 if (chip->info->g2_irqs > 0)
5670 mv88e6xxx_g2_irq_free(chip);
5672 if (chip->irq > 0)
5673 mv88e6xxx_g1_irq_free(chip);
5675 mv88e6xxx_irq_poll_free(chip);