Lines Matching defs:ops
406 if (chip->info->ops->port_set_rgmii_delay) {
407 err = chip->info->ops->port_set_rgmii_delay(chip, port,
413 if (chip->info->ops->port_set_cmode) {
414 err = chip->info->ops->port_set_cmode(chip, port,
429 if (!chip->info->ops->port_set_link)
433 err = chip->info->ops->port_set_link(chip, port, LINK_FORCED_DOWN);
437 if (chip->info->ops->port_set_speed_duplex) {
438 err = chip->info->ops->port_set_speed_duplex(chip, port,
444 if (speed == SPEED_MAX && chip->info->ops->port_max_speed_mode)
445 mode = chip->info->ops->port_max_speed_mode(port);
447 if (chip->info->ops->port_set_pause) {
448 err = chip->info->ops->port_set_pause(chip, port, pause);
455 if (chip->info->ops->port_set_link(chip, port, link))
493 if (lane && chip->info->ops->serdes_pcs_get_state)
494 err = chip->info->ops->serdes_pcs_get_state(chip, port, lane,
508 const struct mv88e6xxx_ops *ops = chip->info->ops;
511 if (ops->serdes_pcs_config) {
514 return ops->serdes_pcs_config(chip, port, lane, mode,
524 const struct mv88e6xxx_ops *ops;
528 ops = chip->info->ops;
530 if (ops->serdes_pcs_an_restart) {
534 err = ops->serdes_pcs_an_restart(chip, port, lane);
546 const struct mv88e6xxx_ops *ops = chip->info->ops;
549 if (!phylink_autoneg_inband(mode) && ops->serdes_pcs_link_up) {
552 return ops->serdes_pcs_link_up(chip, port, lane,
650 if (chip->info->ops->phylink_validate)
651 chip->info->ops->phylink_validate(chip, port, mask, state);
682 chip->info->ops->port_set_link)
683 chip->info->ops->port_set_link(chip, port,
708 if (chip->info->ops->port_set_link &&
711 chip->info->ops->port_set_link(chip, port, LINK_UNFORCED);
727 const struct mv88e6xxx_ops *ops;
730 ops = chip->info->ops;
738 mode == MLO_AN_FIXED) && ops->port_set_link)
739 err = ops->port_set_link(chip, port, LINK_FORCED_DOWN);
754 const struct mv88e6xxx_ops *ops;
757 ops = chip->info->ops;
777 if (ops->port_set_speed_duplex) {
778 err = ops->port_set_speed_duplex(chip, port,
784 if (ops->port_set_link)
785 err = ops->port_set_link(chip, port, LINK_FORCED_UP);
797 if (!chip->info->ops->stats_snapshot)
800 return chip->info->ops->stats_snapshot(chip, port);
973 if (chip->info->ops->stats_get_strings)
974 count = chip->info->ops->stats_get_strings(chip, data);
976 if (chip->info->ops->serdes_get_strings) {
978 count = chip->info->ops->serdes_get_strings(chip, port, data);
1028 if (chip->info->ops->stats_get_sset_count)
1029 count = chip->info->ops->stats_get_sset_count(chip);
1033 if (chip->info->ops->serdes_get_sset_count)
1034 serdes_count = chip->info->ops->serdes_get_sset_count(chip,
1119 if (chip->info->ops->stats_get_stats)
1120 count = chip->info->ops->stats_get_stats(chip, port, data);
1123 if (chip->info->ops->serdes_get_stats) {
1125 count = chip->info->ops->serdes_get_stats(chip, port, data);
1156 if (chip->info->ops->serdes_get_regs_len)
1157 len += chip->info->ops->serdes_get_regs_len(chip, port);
1184 if (chip->info->ops->serdes_get_regs)
1185 chip->info->ops->serdes_get_regs(chip, port, &p[i]);
1273 if (chip->info->ops->ieee_pri_map) {
1274 err = chip->info->ops->ieee_pri_map(chip);
1279 if (chip->info->ops->ip_pri_map) {
1280 err = chip->info->ops->ip_pri_map(chip);
1308 if (chip->info->ops->set_cascade_port) {
1310 err = chip->info->ops->set_cascade_port(chip, port);
1333 if (chip->info->ops->rmu_disable)
1334 return chip->info->ops->rmu_disable(chip);
1341 if (chip->info->ops->pot_clear)
1342 return chip->info->ops->pot_clear(chip);
1349 if (chip->info->ops->mgmt_rsvd2cpu)
1350 return chip->info->ops->mgmt_rsvd2cpu(chip);
1375 if (!chip->info->ops->irl_init_all)
1382 err = chip->info->ops->irl_init_all(chip, port);
1392 if (chip->info->ops->set_switch_mac) {
1397 return chip->info->ops->set_switch_mac(chip, addr);
1467 if (!chip->info->ops->vtu_getnext)
1470 return chip->info->ops->vtu_getnext(chip, entry);
1476 if (!chip->info->ops->vtu_loadpurge)
1479 return chip->info->ops->vtu_loadpurge(chip, entry);
1707 if (!chip->info->ops->port_set_policy)
1741 return chip->info->ops->port_set_policy(chip, port, mapping, action);
2301 if (chip->info->ops->reset)
2302 return chip->info->ops->reset(chip);
2319 if (chip->info->ops->get_eeprom)
2327 if (chip->info->ops->get_eeprom)
2370 if (!chip->info->ops->port_set_frame_mode)
2377 err = chip->info->ops->port_set_frame_mode(chip, port, frame);
2381 if (chip->info->ops->port_set_ether_type)
2382 return chip->info->ops->port_set_ether_type(chip, port, etype);
2441 if (chip->info->ops->port_set_egress_floods)
2442 return chip->info->ops->port_set_egress_floods(chip, port,
2551 if (chip->info->ops->port_set_upstream_port) {
2552 err = chip->info->ops->port_set_upstream_port(chip, port,
2559 if (chip->info->ops->set_cpu_port) {
2560 err = chip->info->ops->set_cpu_port(chip,
2566 if (chip->info->ops->set_egress_port) {
2567 err = chip->info->ops->set_egress_port(chip,
2573 err = chip->info->ops->set_egress_port(chip,
2663 if (chip->info->ops->port_set_jumbo_size) {
2664 err = chip->info->ops->port_set_jumbo_size(chip, port, 10218);
2690 if (chip->info->ops->port_pause_limit) {
2691 err = chip->info->ops->port_pause_limit(chip, port, 0, 0);
2696 if (chip->info->ops->port_disable_learn_limit) {
2697 err = chip->info->ops->port_disable_learn_limit(chip, port);
2702 if (chip->info->ops->port_disable_pri_override) {
2703 err = chip->info->ops->port_disable_pri_override(chip, port);
2708 if (chip->info->ops->port_tag_remap) {
2709 err = chip->info->ops->port_tag_remap(chip, port);
2714 if (chip->info->ops->port_egress_rate_limiting) {
2715 err = chip->info->ops->port_egress_rate_limiting(chip, port);
2720 if (chip->info->ops->port_setup_message_port) {
2721 err = chip->info->ops->port_setup_message_port(chip, port);
2748 if (chip->info->ops->port_set_jumbo_size)
2750 else if (chip->info->ops->set_max_frame_size)
2763 if (!chip->info->ops->port_set_jumbo_size &&
2764 !chip->info->ops->set_max_frame_size) {
2775 if (chip->info->ops->port_set_jumbo_size)
2776 ret = chip->info->ops->port_set_jumbo_size(chip, port, new_mtu);
2777 else if (chip->info->ops->set_max_frame_size)
2778 ret = chip->info->ops->set_max_frame_size(chip, new_mtu);
2825 if (chip->info->ops->stats_set_histogram) {
2826 err = chip->info->ops->stats_set_histogram(chip);
2902 if (chip->info->ops->setup_errata) {
2903 err = chip->info->ops->setup_errata(chip);
2910 if (chip->info->ops->port_get_cmode) {
2911 err = chip->info->ops->port_get_cmode(chip, i, &cmode);
3050 if (!chip->info->ops->phy_read)
3054 err = chip->info->ops->phy_read(chip, bus, phy, reg, &val);
3074 if (!chip->info->ops->phy_write)
3078 err = chip->info->ops->phy_write(chip, bus, phy, reg, val);
3214 if (!chip->info->ops->get_eeprom)
3218 err = chip->info->ops->get_eeprom(chip, eeprom, data);
3235 if (!chip->info->ops->set_eeprom)
3242 err = chip->info->ops->set_eeprom(chip, eeprom, data);
4558 .ops = &mv88e6085_ops,
4579 .ops = &mv88e6095_ops,
4602 .ops = &mv88e6097_ops,
4625 .ops = &mv88e6123_ops,
4646 .ops = &mv88e6131_ops,
4670 .ops = &mv88e6141_ops,
4694 .ops = &mv88e6161_ops,
4718 .ops = &mv88e6165_ops,
4741 .ops = &mv88e6171_ops,
4765 .ops = &mv88e6172_ops,
4788 .ops = &mv88e6175_ops,
4812 .ops = &mv88e6176_ops,
4833 .ops = &mv88e6185_ops,
4857 .ops = &mv88e6190_ops,
4881 .ops = &mv88e6190x_ops,
4905 .ops = &mv88e6191_ops,
4932 .ops = &mv88e6250_ops,
4957 .ops = &mv88e6240_ops,
4979 .ops = &mv88e6250_ops,
5003 .ops = &mv88e6290_ops,
5028 .ops = &mv88e6320_ops,
5052 .ops = &mv88e6321_ops,
5077 .ops = &mv88e6341_ops,
5100 .ops = &mv88e6350_ops,
5123 .ops = &mv88e6351_ops,
5148 .ops = &mv88e6352_ops,
5172 .ops = &mv88e6390_ops,
5196 .ops = &mv88e6390x_ops,
5318 if (!chip->info->ops->set_egress_port)
5335 err = chip->info->ops->set_egress_port(chip,
5370 if (chip->info->ops->set_egress_port(chip,
5387 if (chip->info->ops->port_set_egress_floods)
5388 err = chip->info->ops->port_set_egress_floods(chip, port,
5465 ds->ops = &mv88e6xxx_switch_ops;
5568 if (chip->info->ops->get_eeprom) {