Lines Matching refs:port
184 /* MT7530 uses 31 as the pseudo port */
211 /* MT7530 uses 31 as the pseudo port */
607 static int mt7530_phy_read(struct dsa_switch *ds, int port, int regnum)
611 return mdiobus_read_nested(priv->bus, port, regnum);
614 static int mt7530_phy_write(struct dsa_switch *ds, int port, int regnum,
619 return mdiobus_write_nested(priv->bus, port, regnum, val);
623 mt7531_ind_c45_phy_read(struct mt7530_priv *priv, int port, int devad,
642 reg = MT7531_MDIO_CL45_ADDR | MT7531_MDIO_PHY_ADDR(port) |
653 reg = MT7531_MDIO_CL45_READ | MT7531_MDIO_PHY_ADDR(port) |
672 mt7531_ind_c45_phy_write(struct mt7530_priv *priv, int port, int devad,
691 reg = MT7531_MDIO_CL45_ADDR | MT7531_MDIO_PHY_ADDR(port) |
702 reg = MT7531_MDIO_CL45_WRITE | MT7531_MDIO_PHY_ADDR(port) |
720 mt7531_ind_c22_phy_read(struct mt7530_priv *priv, int port, int regnum)
738 val = MT7531_MDIO_CL22_READ | MT7531_MDIO_PHY_ADDR(port) |
758 mt7531_ind_c22_phy_write(struct mt7530_priv *priv, int port, int regnum,
777 reg = MT7531_MDIO_CL22_WRITE | MT7531_MDIO_PHY_ADDR(port) |
796 mt7531_ind_phy_read(struct dsa_switch *ds, int port, int regnum)
804 ret = mt7531_ind_c45_phy_read(priv, port, devad,
807 ret = mt7531_ind_c22_phy_read(priv, port, regnum);
814 mt7531_ind_phy_write(struct dsa_switch *ds, int port, int regnum,
823 ret = mt7531_ind_c45_phy_write(priv, port, devad,
827 ret = mt7531_ind_c22_phy_write(priv, port, regnum, data);
834 mt7530_get_strings(struct dsa_switch *ds, int port, u32 stringset,
848 mt7530_get_ethtool_stats(struct dsa_switch *ds, int port,
858 reg = MT7530_PORT_MIB_COUNTER(port) + mib->offset;
869 mt7530_get_sset_count(struct dsa_switch *ds, int port, int sset)
899 /* Setup the MAC by default for the cpu port */
949 mt753x_cpu_port_enable(struct dsa_switch *ds, int port)
954 /* Setup max capability of CPU port at first */
956 ret = priv->info->cpu_port_config(ds, port);
961 /* Enable Mediatek header mode on the cpu port */
962 mt7530_write(priv, MT7530_PVC_P(port),
965 /* Unknown multicast frame forwarding to the cpu port */
966 mt7530_rmw(priv, MT7530_MFC, UNM_FFP_MASK, UNM_FFP(BIT(port)));
968 /* Set CPU port number */
970 mt7530_rmw(priv, MT7530_MFC, CPU_MASK, CPU_EN | CPU_PORT(port));
972 /* CPU port gets connected to all user ports of
975 mt7530_write(priv, MT7530_PCR_P(port),
982 mt7530_port_enable(struct dsa_switch *ds, int port,
989 /* Allow the user port gets connected to the cpu port and also
990 * restore the port matrix if the port is the member of a certain
993 priv->ports[port].pm |= PCR_MATRIX(BIT(MT7530_CPU_PORT));
994 priv->ports[port].enable = true;
995 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK,
996 priv->ports[port].pm);
997 mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK);
1005 mt7530_port_disable(struct dsa_switch *ds, int port)
1011 /* Clear up all port matrix which could be restored in the next
1012 * enablement for the port.
1014 priv->ports[port].enable = false;
1015 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK,
1017 mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK);
1023 mt7530_stp_state_set(struct dsa_switch *ds, int port, u8 state)
1047 mt7530_rmw(priv, MT7530_SSP_P(port), FID_PST_MASK, stp_state);
1051 mt7530_port_bridge_join(struct dsa_switch *ds, int port,
1061 /* Add this port to the port matrix of the other ports in the
1062 * same bridge. If the port is disabled, port matrix is kept
1063 * and not being setup until the port becomes enabled.
1065 if (dsa_is_user_port(ds, i) && i != port) {
1070 PCR_MATRIX(BIT(port)));
1071 priv->ports[i].pm |= PCR_MATRIX(BIT(port));
1077 /* Add the all other ports to this port matrix. */
1078 if (priv->ports[port].enable)
1079 mt7530_rmw(priv, MT7530_PCR_P(port),
1081 priv->ports[port].pm |= PCR_MATRIX(port_bitmap);
1089 mt7530_port_set_vlan_unaware(struct dsa_switch *ds, int port)
1095 /* When a port is removed from the bridge, the port would be set up
1097 * port.
1099 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK,
1101 mt7530_rmw(priv, MT7530_PVC_P(port), VLAN_ATTR_MASK | PVC_EG_TAG_MASK,
1113 /* CPU port also does the same thing until all user ports belonging to
1114 * the CPU port get out of VLAN filtering mode.
1125 mt7530_port_set_vlan_aware(struct dsa_switch *ds, int port)
1130 * table lookup. CPU port is set to fallback mode to let untagged
1133 if (dsa_is_cpu_port(ds, port))
1134 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK,
1137 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK,
1140 /* Set the port as a user port which is to be able to recognize VID
1143 mt7530_rmw(priv, MT7530_PVC_P(port), VLAN_ATTR_MASK | PVC_EG_TAG_MASK,
1149 mt7530_port_bridge_leave(struct dsa_switch *ds, int port,
1158 /* Remove this port from the port matrix of the other ports
1159 * in the same bridge. If the port is disabled, port matrix
1160 * is kept and not being setup until the port becomes enabled.
1162 if (dsa_is_user_port(ds, i) && i != port) {
1167 PCR_MATRIX(BIT(port)));
1168 priv->ports[i].pm &= ~PCR_MATRIX(BIT(port));
1172 /* Set the cpu port to be the only one in the port matrix of
1173 * this port.
1175 if (priv->ports[port].enable)
1176 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK,
1178 priv->ports[port].pm = PCR_MATRIX(BIT(MT7530_CPU_PORT));
1184 mt7530_port_fdb_add(struct dsa_switch *ds, int port,
1189 u8 port_mask = BIT(port);
1200 mt7530_port_fdb_del(struct dsa_switch *ds, int port,
1205 u8 port_mask = BIT(port);
1216 mt7530_port_fdb_dump(struct dsa_switch *ds, int port,
1234 if (_fdb.port_mask & BIT(port)) {
1278 mt7530_port_vlan_filtering(struct dsa_switch *ds, int port,
1286 /* The port is being kept as VLAN-unaware port when bridge is
1288 * port and the corresponding CPU port is required the setup
1289 * for becoming a VLAN-aware port.
1291 mt7530_port_set_vlan_aware(ds, port);
1294 mt7530_port_set_vlan_unaware(ds, port);
1301 mt7530_port_vlan_prepare(struct dsa_switch *ds, int port,
1316 new_members = entry->old_members | BIT(entry->port) |
1320 * VLAN and joining the port as one of the port members.
1326 * port inside the VLAN.
1331 ETAG_CTRL_P_MASK(entry->port),
1332 ETAG_CTRL_P(entry->port, val));
1334 /* CPU port is always taken as a tagged port for serving more than one
1352 new_members = entry->old_members & ~BIT(entry->port);
1361 /* If certain member apart from CPU port is still alive in the VLAN,
1397 mt7530_port_vlan_add(struct dsa_switch *ds, int port,
1409 mt7530_hw_vlan_entry_init(&new_entry, port, untagged);
1415 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK,
1417 priv->ports[port].pvid = vlan->vid_end;
1424 mt7530_port_vlan_del(struct dsa_switch *ds, int port,
1433 pvid = priv->ports[port].pvid;
1435 mt7530_hw_vlan_entry_init(&target_entry, port, 0);
1439 /* PVID is being restored to the default whenever the PVID port
1446 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, pvid);
1447 priv->ports[port].pvid = pvid;
1466 static int mt753x_port_mirror_add(struct dsa_switch *ds, int port,
1475 if ((ingress ? priv->mirror_rx : priv->mirror_tx) & BIT(port))
1480 /* MT7530 only supports one monitor port */
1491 val = mt7530_read(priv, MT7530_PCR_P(port));
1494 priv->mirror_rx |= BIT(port);
1497 priv->mirror_tx |= BIT(port);
1499 mt7530_write(priv, MT7530_PCR_P(port), val);
1504 static void mt753x_port_mirror_del(struct dsa_switch *ds, int port,
1510 val = mt7530_read(priv, MT7530_PCR_P(port));
1513 priv->mirror_rx &= ~BIT(port);
1516 priv->mirror_tx &= ~BIT(port);
1518 mt7530_write(priv, MT7530_PCR_P(port), val);
1528 mtk_get_tag_protocol(struct dsa_switch *ds, int port,
1533 if (port != MT7530_CPU_PORT) {
1535 "port not matched with tagging CPU port\n");
1641 /* Setup port 5 */
1772 /* BPDU to CPU port */
1811 mt7530_phy_mode_supported(struct dsa_switch *ds, int port,
1816 switch (port) {
1821 case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */
1827 case 6: /* 1st cpu port */
1833 dev_err(priv->dev, "%s: unsupported port: %i\n", __func__,
1834 port);
1841 static bool mt7531_is_rgmii_port(struct mt7530_priv *priv, u32 port)
1843 return (port == 5) && (priv->p5_intf_sel != P5_INTF_SEL_GMAC5_SGMII);
1847 mt7531_phy_mode_supported(struct dsa_switch *ds, int port,
1852 switch (port) {
1857 case 5: /* 2nd cpu port supports either rgmii or sgmii/8023z */
1858 if (mt7531_is_rgmii_port(priv, port))
1861 case 6: /* 1st cpu port supports sgmii/8023z only */
1867 dev_err(priv->dev, "%s: unsupported port: %i\n", __func__,
1868 port);
1876 mt753x_phy_mode_supported(struct dsa_switch *ds, int port,
1881 return priv->info->phy_mode_supported(ds, port, state);
1893 mt7530_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
1899 if (port != 5)
1907 static int mt7531_rgmii_setup(struct mt7530_priv *priv, u32 port,
1913 if (!mt7531_is_rgmii_port(priv, port)) {
1914 dev_err(priv->dev, "RGMII mode is not available for port %d\n",
1915 port);
1954 static void mt7531_sgmii_validate(struct mt7530_priv *priv, int port,
1960 if (port == 6) {
1967 mt7531_sgmii_link_up_force(struct dsa_switch *ds, int port,
1980 val = mt7530_read(priv, MT7531_SGMII_MODE(port));
2002 mt7530_write(priv, MT7531_SGMII_MODE(port), val);
2005 static bool mt753x_is_mac_port(u32 port)
2007 return (port == 5 || port == 6);
2010 static int mt7531_sgmii_setup_mode_force(struct mt7530_priv *priv, u32 port,
2015 if (!mt753x_is_mac_port(port))
2018 mt7530_set(priv, MT7531_QPHY_PWR_STATE_CTRL(port),
2021 val = mt7530_read(priv, MT7531_PHYA_CTRL_SIGNAL3(port));
2028 mt7530_write(priv, MT7531_PHYA_CTRL_SIGNAL3(port), val);
2030 mt7530_clear(priv, MT7531_PCS_CONTROL_1(port), MT7531_SGMII_AN_ENABLE);
2035 mt7530_rmw(priv, MT7531_SGMII_MODE(port),
2039 mt7530_write(priv, MT7531_QPHY_PWR_STATE_CTRL(port), 0);
2044 static int mt7531_sgmii_setup_mode_an(struct mt7530_priv *priv, int port,
2047 if (!mt753x_is_mac_port(port))
2050 mt7530_set(priv, MT7531_QPHY_PWR_STATE_CTRL(port),
2053 mt7530_rmw(priv, MT7531_PHYA_CTRL_SIGNAL3(port),
2056 mt7530_set(priv, MT7531_SGMII_MODE(port),
2060 mt7530_rmw(priv, MT7531_PCS_SPEED_ABILITY(port),
2063 mt7530_set(priv, MT7531_PCS_CONTROL_1(port), MT7531_SGMII_AN_ENABLE);
2065 mt7530_set(priv, MT7531_PCS_CONTROL_1(port), MT7531_SGMII_AN_RESTART);
2067 mt7530_write(priv, MT7531_QPHY_PWR_STATE_CTRL(port), 0);
2072 static void mt7531_sgmii_restart_an(struct dsa_switch *ds, int port)
2078 val = mt7530_read(priv, MT7531_PCS_CONTROL_1(port));
2081 mt7530_write(priv, MT7531_PCS_CONTROL_1(port), val);
2086 mt7531_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
2093 if (!mt753x_is_mac_port(port)) {
2094 dev_err(priv->dev, "port %d is not a MAC port\n", port);
2103 dp = dsa_to_port(ds, port);
2105 return mt7531_rgmii_setup(priv, port, interface, phydev);
2107 return mt7531_sgmii_setup_mode_an(priv, port, interface);
2114 return mt7531_sgmii_setup_mode_force(priv, port, interface);
2123 mt753x_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
2128 return priv->info->mac_port_config(ds, port, mode, state->interface);
2132 mt753x_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
2138 if (!mt753x_phy_mode_supported(ds, port, state))
2141 switch (port) {
2146 case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */
2150 if (mt753x_mac_config(ds, port, mode, state) < 0)
2156 case 6: /* 1st cpu port */
2162 if (mt753x_mac_config(ds, port, mode, state) < 0)
2169 dev_err(ds->dev, "%s: unsupported %s port: %i\n",
2170 __func__, phy_modes(state->interface), port);
2181 mcr_cur = mt7530_read(priv, MT7530_PMCR_P(port));
2188 if (port == 5 && dsa_is_user_port(ds, 5))
2192 mt7530_write(priv, MT7530_PMCR_P(port), mcr_new);
2196 mt753x_phylink_mac_an_restart(struct dsa_switch *ds, int port)
2203 priv->info->mac_pcs_an_restart(ds, port);
2206 static void mt753x_phylink_mac_link_down(struct dsa_switch *ds, int port,
2212 mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK);
2215 static void mt753x_mac_pcs_link_up(struct dsa_switch *ds, int port,
2224 priv->info->mac_pcs_link_up(ds, port, mode, interface, speed, duplex);
2227 static void mt753x_phylink_mac_link_up(struct dsa_switch *ds, int port,
2237 mt753x_mac_pcs_link_up(ds, port, mode, interface, speed, duplex);
2266 mt7530_set(priv, MT7530_PMCR_P(port), mcr);
2270 mt7531_cpu_port_config(struct dsa_switch *ds, int port)
2277 switch (port) {
2279 if (mt7531_is_rgmii_port(priv, port))
2300 ret = mt7531_mac_config(ds, port, MLO_AN_FIXED, interface);
2303 mt7530_write(priv, MT7530_PMCR_P(port),
2305 mt753x_phylink_mac_link_up(ds, port, MLO_AN_FIXED, interface, NULL,
2312 mt7530_mac_port_validate(struct dsa_switch *ds, int port,
2317 static void mt7531_mac_port_validate(struct dsa_switch *ds, int port,
2322 mt7531_sgmii_validate(priv, port, supported);
2326 mt753x_phylink_validate(struct dsa_switch *ds, int port,
2334 !mt753x_phy_mode_supported(ds, port, state)) {
2356 priv->info->mac_port_validate(ds, port, mask);
2371 mt7530_phylink_mac_link_state(struct dsa_switch *ds, int port,
2377 if (port < 0 || port >= MT7530_NUM_PORTS)
2380 pmsr = mt7530_read(priv, MT7530_PMSR_P(port));
2411 mt7531_sgmii_pcs_get_state_an(struct mt7530_priv *priv, int port,
2417 status = mt7530_read(priv, MT7531_PCS_CONTROL_1(port));
2421 val = mt7530_read(priv, MT7531_PCS_SPEED_ABILITY(port));
2450 mt7531_phylink_mac_link_state(struct dsa_switch *ds, int port,
2456 return mt7531_sgmii_pcs_get_state_an(priv, port, state);
2462 mt753x_phylink_mac_link_state(struct dsa_switch *ds, int port,
2467 return priv->info->mac_port_get_state(ds, port, state);
2479 mt753x_phy_read(struct dsa_switch *ds, int port, int regnum)
2483 return priv->info->phy_read(ds, port, regnum);
2487 mt753x_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val)
2491 return priv->info->phy_write(ds, port, regnum, val);