Lines Matching defs:val
133 core_write(struct mt7530_priv *priv, u32 reg, u32 val)
139 core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val);
148 u32 val;
152 val = core_read_mmd_indirect(priv, reg, MDIO_MMD_VEND2);
153 val &= ~mask;
154 val |= set;
155 core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val);
161 core_set(struct mt7530_priv *priv, u32 reg, u32 val)
163 core_rmw(priv, reg, 0, val);
167 core_clear(struct mt7530_priv *priv, u32 reg, u32 val)
169 core_rmw(priv, reg, val, 0);
173 mt7530_mii_write(struct mt7530_priv *priv, u32 reg, u32 val)
181 lo = val & 0xffff;
182 hi = val >> 16;
226 mt7530_write(struct mt7530_priv *priv, u32 reg, u32 val)
232 mt7530_mii_write(priv, reg, val);
247 u32 val;
251 val = mt7530_mii_read(p->priv, p->reg);
255 return val;
272 u32 val;
276 val = mt7530_mii_read(priv, reg);
277 val &= ~mask;
278 val |= set;
279 mt7530_mii_write(priv, reg, val);
285 mt7530_set(struct mt7530_priv *priv, u32 reg, u32 val)
287 mt7530_rmw(priv, reg, 0, val);
291 mt7530_clear(struct mt7530_priv *priv, u32 reg, u32 val)
293 mt7530_rmw(priv, reg, val, 0);
299 u32 val;
304 val = ATC_BUSY | ATC_MAT(0) | cmd;
305 mt7530_write(priv, MT7530_ATC, val);
308 ret = readx_poll_timeout(_mt7530_read, &p, val,
309 !(val & ATC_BUSY), 20, 20000);
318 val = mt7530_read(priv, MT7530_ATC);
319 if ((cmd == MT7530_FDB_READ) && (val & ATC_INVALID))
323 *rsp = val;
495 u32 val;
497 val = mt7530_read(priv, MT7531_TOP_SIG_SR);
499 return (val & PAD_DUAL_SGMII_EN) != 0;
514 u32 val;
519 val = mt7530_read(priv, MT7531_CREV);
522 if ((val & CHIP_REV_M) > 0)
529 val = mt7530_read(priv, MT7531_PLLGP_EN);
530 val &= ~EN_COREPLL;
531 mt7530_write(priv, MT7531_PLLGP_EN, val);
534 val = mt7530_read(priv, MT7531_PLLGP_EN);
535 val |= SW_CLKSW;
536 mt7530_write(priv, MT7531_PLLGP_EN, val);
538 val = mt7530_read(priv, MT7531_PLLGP_CR0);
539 val &= ~RG_COREPLL_EN;
540 mt7530_write(priv, MT7531_PLLGP_CR0, val);
543 val = mt7530_read(priv, MT7531_PLLGP_EN);
544 val |= SW_PLLGP;
545 mt7530_write(priv, MT7531_PLLGP_EN, val);
548 val = mt7530_read(priv, MT7531_PLLGP_CR0);
549 val &= ~RG_COREPLL_POSDIV_M;
550 val |= 2 << RG_COREPLL_POSDIV_S;
551 mt7530_write(priv, MT7531_PLLGP_CR0, val);
556 val = mt7530_read(priv, MT7531_PLLGP_CR0);
557 val &= ~RG_COREPLL_SDM_PCW_M;
558 val |= 0x140000 << RG_COREPLL_SDM_PCW_S;
559 mt7530_write(priv, MT7531_PLLGP_CR0, val);
562 val = mt7530_read(priv, MT7531_PLLGP_CR0);
563 val &= ~RG_COREPLL_SDM_PCW_M;
564 val |= 0x190000 << RG_COREPLL_SDM_PCW_S;
565 mt7530_write(priv, MT7531_PLLGP_CR0, val);
570 val = mt7530_read(priv, MT7531_PLLGP_CR0);
571 val |= RG_COREPLL_SDM_PCW_CHG;
572 mt7530_write(priv, MT7531_PLLGP_CR0, val);
577 val = mt7530_read(priv, MT7531_PLLGP_CR0);
578 val &= ~RG_COREPLL_SDM_PCW_CHG;
579 mt7530_write(priv, MT7531_PLLGP_CR0, val);
588 val = mt7530_read(priv, MT7531_PLLGP_CR0);
589 val |= RG_COREPLL_EN;
590 mt7530_write(priv, MT7531_PLLGP_CR0, val);
592 val = mt7530_read(priv, MT7531_PLLGP_EN);
593 val |= EN_COREPLL;
594 mt7530_write(priv, MT7531_PLLGP_EN, val);
615 u16 val)
619 return mdiobus_write_nested(priv->bus, port, regnum, val);
628 u32 reg, val;
635 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
636 !(val & MT7531_PHY_ACS_ST), 20, 100000);
646 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
647 !(val & MT7531_PHY_ACS_ST), 20, 100000);
657 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
658 !(val & MT7531_PHY_ACS_ST), 20, 100000);
664 ret = val & MT7531_MDIO_RW_DATA_MASK;
677 u32 val, reg;
684 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
685 !(val & MT7531_PHY_ACS_ST), 20, 100000);
695 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
696 !(val & MT7531_PHY_ACS_ST), 20, 100000);
706 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
707 !(val & MT7531_PHY_ACS_ST), 20, 100000);
725 u32 val;
731 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
732 !(val & MT7531_PHY_ACS_ST), 20, 100000);
738 val = MT7531_MDIO_CL22_READ | MT7531_MDIO_PHY_ADDR(port) |
741 mt7530_mii_write(priv, MT7531_PHY_IAC, val | MT7531_PHY_ACS_ST);
743 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
744 !(val & MT7531_PHY_ACS_ST), 20, 100000);
750 ret = val & MT7531_MDIO_RW_DATA_MASK;
881 int val;
885 val = mt7530_read(priv, MT7530_MHWTRAP);
887 val |= MHWTRAP_MANUAL | MHWTRAP_P5_MAC_SEL | MHWTRAP_P5_DIS;
888 val &= ~MHWTRAP_P5_RGMII_MODE & ~MHWTRAP_PHY0_SEL;
893 val |= MHWTRAP_PHY0_SEL;
897 val &= ~MHWTRAP_P5_MAC_SEL & ~MHWTRAP_P5_DIS;
904 val &= ~MHWTRAP_P5_DIS;
917 val |= MHWTRAP_P5_RGMII_MODE;
937 mt7530_write(priv, MT7530_MHWTRAP, val);
940 val, p5_intf_modes(priv->p5_intf_sel), phy_modes(interface));
1254 u32 val;
1257 val = VTCR_BUSY | VTCR_FUNC(cmd) | vid;
1258 mt7530_write(priv, MT7530_VTCR, val);
1261 ret = readx_poll_timeout(_mt7530_read, &p, val,
1262 !(val & VTCR_BUSY), 20, 20000);
1268 val = mt7530_read(priv, MT7530_VTCR);
1269 if (val & VTCR_INVALID) {
1314 u32 val;
1322 val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) | VLAN_VALID;
1323 mt7530_write(priv, MT7530_VAWD1, val);
1328 val = entry->untagged ? MT7530_VLAN_EGRESS_UNTAG :
1332 ETAG_CTRL_P(entry->port, val));
1350 u32 val;
1354 val = mt7530_read(priv, MT7530_VAWD1);
1355 if (!(val & VLAN_VALID)) {
1366 val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) |
1368 mt7530_write(priv, MT7530_VAWD1, val);
1380 u32 val;
1385 val = mt7530_read(priv, MT7530_VAWD1);
1387 entry->old_members = (val >> PORT_MEM_SHFT) & PORT_MEM_MASK;
1454 static int mt753x_mirror_port_get(unsigned int id, u32 val)
1456 return (id == ID_MT7531) ? MT7531_MIRROR_PORT_GET(val) :
1457 MIRROR_PORT(val);
1460 static int mt753x_mirror_port_set(unsigned int id, u32 val)
1462 return (id == ID_MT7531) ? MT7531_MIRROR_PORT_SET(val) :
1463 MIRROR_PORT(val);
1472 u32 val;
1478 val = mt7530_read(priv, MT753X_MIRROR_REG(priv->id));
1481 monitor_port = mt753x_mirror_port_get(priv->id, val);
1482 if (val & MT753X_MIRROR_EN(priv->id) &&
1486 val |= MT753X_MIRROR_EN(priv->id);
1487 val &= ~MT753X_MIRROR_MASK(priv->id);
1488 val |= mt753x_mirror_port_set(priv->id, mirror->to_local_port);
1489 mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val);
1491 val = mt7530_read(priv, MT7530_PCR_P(port));
1493 val |= PORT_RX_MIR;
1496 val |= PORT_TX_MIR;
1499 mt7530_write(priv, MT7530_PCR_P(port), val);
1508 u32 val;
1510 val = mt7530_read(priv, MT7530_PCR_P(port));
1512 val &= ~PORT_RX_MIR;
1515 val &= ~PORT_TX_MIR;
1518 mt7530_write(priv, MT7530_PCR_P(port), val);
1521 val = mt7530_read(priv, MT753X_MIRROR_REG(priv->id));
1522 val &= ~MT753X_MIRROR_EN(priv->id);
1523 mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val);
1551 u32 id, val;
1594 ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0,
1614 val = mt7530_read(priv, MT7530_MHWTRAP);
1615 val &= ~MHWTRAP_P6_DIS & ~MHWTRAP_PHY_ACCESS;
1616 val |= MHWTRAP_MANUAL;
1617 mt7530_write(priv, MT7530_MHWTRAP, val);
1699 u32 val, id;
1717 ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0,
1765 val = mt7531_ind_c45_phy_read(priv, MT753X_CTRL_PHY_ADDR,
1767 val |= MT7531_PHY_PLL_BYPASS_MODE;
1768 val &= ~MT7531_PHY_PLL_OFF;
1770 CORE_PLL_GROUP4, val);
1911 u32 val;
1919 val = mt7530_read(priv, MT7531_CLKGEN_CTRL);
1920 val |= GP_CLK_EN;
1921 val &= ~GP_MODE_MASK;
1922 val |= GP_MODE(MT7531_GP_MODE_RGMII);
1923 val &= ~CLK_SKEW_IN_MASK;
1924 val |= CLK_SKEW_IN(MT7531_CLK_SKEW_NO_CHG);
1925 val &= ~CLK_SKEW_OUT_MASK;
1926 val |= CLK_SKEW_OUT(MT7531_CLK_SKEW_NO_CHG);
1927 val |= TXCLK_NO_REVERSE | RXCLK_NO_DELAY;
1931 val &= ~(TXCLK_NO_REVERSE | RXCLK_NO_DELAY);
1934 val |= TXCLK_NO_REVERSE;
1935 val |= RXCLK_NO_DELAY;
1938 val |= TXCLK_NO_REVERSE;
1941 val |= RXCLK_NO_DELAY;
1949 mt7530_write(priv, MT7531_CLKGEN_CTRL, val);
1972 unsigned int val;
1980 val = mt7530_read(priv, MT7531_SGMII_MODE(port));
1981 val &= ~MT7531_SGMII_IF_MODE_MASK;
1985 val |= MT7531_SGMII_FORCE_SPEED_10;
1988 val |= MT7531_SGMII_FORCE_SPEED_100;
1991 val |= MT7531_SGMII_FORCE_SPEED_1000;
2000 val |= MT7531_SGMII_FORCE_HALF_DUPLEX;
2002 mt7530_write(priv, MT7531_SGMII_MODE(port), val);
2013 u32 val;
2021 val = mt7530_read(priv, MT7531_PHYA_CTRL_SIGNAL3(port));
2022 val &= ~MT7531_RG_TPHY_SPEED_MASK;
2026 val |= (interface == PHY_INTERFACE_MODE_2500BASEX) ?
2028 mt7530_write(priv, MT7531_PHYA_CTRL_SIGNAL3(port), val);
2075 u32 val;
2078 val = mt7530_read(priv, MT7531_PCS_CONTROL_1(port));
2079 if (val & MT7531_SGMII_AN_ENABLE) {
2080 val |= MT7531_SGMII_AN_RESTART;
2081 mt7530_write(priv, MT7531_PCS_CONTROL_1(port), val);
2414 u32 status, val;
2421 val = mt7530_read(priv, MT7531_PCS_SPEED_ABILITY(port));
2422 config_reg = val >> 16;
2487 mt753x_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val)
2491 return priv->info->phy_write(ds, port, regnum, val);