Lines Matching refs:dev
67 static void ksz_cfg(struct ksz_device *dev, u32 addr, u8 bits, bool set)
69 regmap_update_bits(dev->regmap[0], addr, bits, set ? bits : 0);
72 static void ksz_port_cfg(struct ksz_device *dev, int port, int offset, u8 bits,
75 regmap_update_bits(dev->regmap[0], PORT_CTRL_ADDR(port, offset),
79 static void ksz9477_cfg32(struct ksz_device *dev, u32 addr, u32 bits, bool set)
81 regmap_update_bits(dev->regmap[2], addr, bits, set ? bits : 0);
84 static void ksz9477_port_cfg32(struct ksz_device *dev, int port, int offset,
87 regmap_update_bits(dev->regmap[2], PORT_CTRL_ADDR(port, offset),
91 static int ksz9477_wait_vlan_ctrl_ready(struct ksz_device *dev)
95 return regmap_read_poll_timeout(dev->regmap[0], REG_SW_VLAN_CTRL,
99 static int ksz9477_get_vlan_table(struct ksz_device *dev, u16 vid,
104 mutex_lock(&dev->vlan_mutex);
106 ksz_write16(dev, REG_SW_VLAN_ENTRY_INDEX__2, vid & VLAN_INDEX_M);
107 ksz_write8(dev, REG_SW_VLAN_CTRL, VLAN_READ | VLAN_START);
110 ret = ksz9477_wait_vlan_ctrl_ready(dev);
112 dev_dbg(dev->dev, "Failed to read vlan table\n");
116 ksz_read32(dev, REG_SW_VLAN_ENTRY__4, &vlan_table[0]);
117 ksz_read32(dev, REG_SW_VLAN_ENTRY_UNTAG__4, &vlan_table[1]);
118 ksz_read32(dev, REG_SW_VLAN_ENTRY_PORTS__4, &vlan_table[2]);
120 ksz_write8(dev, REG_SW_VLAN_CTRL, 0);
123 mutex_unlock(&dev->vlan_mutex);
128 static int ksz9477_set_vlan_table(struct ksz_device *dev, u16 vid,
133 mutex_lock(&dev->vlan_mutex);
135 ksz_write32(dev, REG_SW_VLAN_ENTRY__4, vlan_table[0]);
136 ksz_write32(dev, REG_SW_VLAN_ENTRY_UNTAG__4, vlan_table[1]);
137 ksz_write32(dev, REG_SW_VLAN_ENTRY_PORTS__4, vlan_table[2]);
139 ksz_write16(dev, REG_SW_VLAN_ENTRY_INDEX__2, vid & VLAN_INDEX_M);
140 ksz_write8(dev, REG_SW_VLAN_CTRL, VLAN_START | VLAN_WRITE);
143 ret = ksz9477_wait_vlan_ctrl_ready(dev);
145 dev_dbg(dev->dev, "Failed to write vlan table\n");
149 ksz_write8(dev, REG_SW_VLAN_CTRL, 0);
152 dev->vlan_cache[vid].table[0] = vlan_table[0];
153 dev->vlan_cache[vid].table[1] = vlan_table[1];
154 dev->vlan_cache[vid].table[2] = vlan_table[2];
157 mutex_unlock(&dev->vlan_mutex);
162 static void ksz9477_read_table(struct ksz_device *dev, u32 *table)
164 ksz_read32(dev, REG_SW_ALU_VAL_A, &table[0]);
165 ksz_read32(dev, REG_SW_ALU_VAL_B, &table[1]);
166 ksz_read32(dev, REG_SW_ALU_VAL_C, &table[2]);
167 ksz_read32(dev, REG_SW_ALU_VAL_D, &table[3]);
170 static void ksz9477_write_table(struct ksz_device *dev, u32 *table)
172 ksz_write32(dev, REG_SW_ALU_VAL_A, table[0]);
173 ksz_write32(dev, REG_SW_ALU_VAL_B, table[1]);
174 ksz_write32(dev, REG_SW_ALU_VAL_C, table[2]);
175 ksz_write32(dev, REG_SW_ALU_VAL_D, table[3]);
178 static int ksz9477_wait_alu_ready(struct ksz_device *dev)
182 return regmap_read_poll_timeout(dev->regmap[2], REG_SW_ALU_CTRL__4,
186 static int ksz9477_wait_alu_sta_ready(struct ksz_device *dev)
190 return regmap_read_poll_timeout(dev->regmap[2],
196 static int ksz9477_reset_switch(struct ksz_device *dev)
202 ksz_cfg(dev, REG_SW_OPERATION, SW_RESET, true);
205 regmap_update_bits(dev->regmap[0], REG_SW_GLOBAL_SERIAL_CTRL_0,
209 ksz_read8(dev, REG_SW_LUE_CTRL_1, &data8);
212 ksz_write8(dev, REG_SW_LUE_CTRL_1, data8);
215 ksz_write32(dev, REG_SW_INT_MASK__4, SWITCH_INT_MASK);
216 ksz_write32(dev, REG_SW_PORT_INT_MASK__4, 0x7F);
217 ksz_read32(dev, REG_SW_PORT_INT_STATUS__4, &data32);
220 regmap_update_bits(dev->regmap[1], REG_SW_MAC_CTRL_2,
225 if (dev->synclko_125)
226 ksz_write8(dev, REG_SW_GLOBAL_OUTPUT_CTRL__1,
232 static void ksz9477_r_mib_cnt(struct ksz_device *dev, int port, u16 addr,
235 struct ksz_port *p = &dev->ports[port];
244 ksz_pwrite32(dev, port, REG_PORT_MIB_CTRL_STAT__4, data);
246 ret = regmap_read_poll_timeout(dev->regmap[2],
251 dev_dbg(dev->dev, "Failed to get MIB\n");
256 ksz_pread32(dev, port, REG_PORT_MIB_DATA, &data);
260 static void ksz9477_r_mib_pkt(struct ksz_device *dev, int port, u16 addr,
264 ksz9477_r_mib_cnt(dev, port, addr, cnt);
267 static void ksz9477_freeze_mib(struct ksz_device *dev, int port, bool freeze)
270 struct ksz_port *p = &dev->ports[port];
274 ksz_pwrite32(dev, port, REG_PORT_MIB_CTRL_STAT__4, val);
281 static void ksz9477_port_init_cnt(struct ksz_device *dev, int port)
283 struct ksz_port_mib *mib = &dev->ports[port].mib;
287 ksz_pwrite32(dev, port, REG_PORT_MIB_CTRL_STAT__4,
289 ksz_write8(dev, REG_SW_MAC_CTRL_6, SW_MIB_COUNTER_FLUSH);
290 ksz_pwrite32(dev, port, REG_PORT_MIB_CTRL_STAT__4, 0);
294 memset(mib->counters, 0, dev->mib_cnt * sizeof(u64));
302 struct ksz_device *dev = ds->priv;
304 if (dev->features & IS_9893)
311 struct ksz_device *dev = ds->priv;
320 if (addr >= dev->phy_port_cnt) {
321 struct ksz_port *p = &dev->ports[addr];
353 ksz_pread16(dev, addr, 0x100 + (reg << 1), &val);
362 struct ksz_device *dev = ds->priv;
365 if (addr >= dev->phy_port_cnt)
369 if (!(dev->features & GBIT_SUPPORT) && reg == MII_CTRL1000)
371 ksz_pwrite16(dev, addr, 0x100 + (reg << 1), val);
390 static void ksz9477_cfg_port_member(struct ksz_device *dev, int port,
393 ksz_pwrite32(dev, port, REG_PORT_VLAN_MEMBERSHIP__4, member);
394 dev->ports[port].member = member;
400 struct ksz_device *dev = ds->priv;
401 struct ksz_port *p = &dev->ports[port];
404 int forward = dev->member;
406 ksz_pread8(dev, port, P_STP_CTRL, &data);
412 if (port != dev->cpu_port)
417 if (port != dev->cpu_port &&
419 member = dev->host_mask | p->vid_member;
428 if (port == dev->cpu_port)
431 member = dev->host_mask | p->vid_member;
432 mutex_lock(&dev->dev_mutex);
435 if (dev->br_member & (1 << port)) {
436 dev->member |= (1 << port);
437 member = dev->member;
439 mutex_unlock(&dev->dev_mutex);
443 if (port != dev->cpu_port &&
445 member = dev->host_mask | p->vid_member;
448 dev_err(ds->dev, "invalid STP state: %d\n", state);
452 ksz_pwrite8(dev, port, P_STP_CTRL, data);
454 mutex_lock(&dev->dev_mutex);
457 ksz9477_cfg_port_member(dev, port, (u8)member);
461 if (dev->br_member & (1 << port))
462 dev->member &= ~(1 << port);
468 if (forward != dev->member)
469 ksz_update_port_member(dev, port);
470 mutex_unlock(&dev->dev_mutex);
473 static void ksz9477_flush_dyn_mac_table(struct ksz_device *dev, int port)
477 regmap_update_bits(dev->regmap[0], REG_SW_LUE_CTRL_2,
481 if (port < dev->mib_port_cnt) {
483 ksz_pread8(dev, port, P_STP_CTRL, &data);
485 ksz_pwrite8(dev, port, P_STP_CTRL,
487 ksz_cfg(dev, S_FLUSH_TABLE_CTRL, SW_FLUSH_DYN_MAC_TABLE, true);
488 ksz_pwrite8(dev, port, P_STP_CTRL, data);
491 ksz_cfg(dev, S_FLUSH_TABLE_CTRL, SW_FLUSH_STP_TABLE, true);
499 struct ksz_device *dev = ds->priv;
505 ksz_port_cfg(dev, port, REG_PORT_LUE_CTRL,
507 ksz_cfg(dev, REG_SW_LUE_CTRL_0, SW_VLAN_ENABLE, true);
509 ksz_cfg(dev, REG_SW_LUE_CTRL_0, SW_VLAN_ENABLE, false);
510 ksz_port_cfg(dev, port, REG_PORT_LUE_CTRL,
520 struct ksz_device *dev = ds->priv;
526 if (ksz9477_get_vlan_table(dev, vid, vlan_table)) {
527 dev_dbg(dev->dev, "Failed to get vlan table\n");
536 vlan_table[1] &= ~(BIT(dev->cpu_port));
538 vlan_table[2] |= BIT(port) | BIT(dev->cpu_port);
540 if (ksz9477_set_vlan_table(dev, vid, vlan_table)) {
541 dev_dbg(dev->dev, "Failed to set vlan table\n");
547 ksz_pwrite16(dev, port, REG_PORT_DEFAULT_VID, vid);
554 struct ksz_device *dev = ds->priv;
560 ksz_pread16(dev, port, REG_PORT_DEFAULT_VID, &pvid);
564 if (ksz9477_get_vlan_table(dev, vid, vlan_table)) {
565 dev_dbg(dev->dev, "Failed to get vlan table\n");
577 if (ksz9477_set_vlan_table(dev, vid, vlan_table)) {
578 dev_dbg(dev->dev, "Failed to set vlan table\n");
583 ksz_pwrite16(dev, port, REG_PORT_DEFAULT_VID, pvid);
591 struct ksz_device *dev = ds->priv;
596 mutex_lock(&dev->alu_mutex);
601 ksz_write32(dev, REG_SW_ALU_INDEX_0, data);
605 ksz_write32(dev, REG_SW_ALU_INDEX_1, data);
608 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_READ | ALU_START);
611 ret = ksz9477_wait_alu_ready(dev);
613 dev_dbg(dev->dev, "Failed to read ALU\n");
618 ksz9477_read_table(dev, alu_table);
630 ksz9477_write_table(dev, alu_table);
632 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_WRITE | ALU_START);
635 ret = ksz9477_wait_alu_ready(dev);
637 dev_dbg(dev->dev, "Failed to write ALU\n");
640 mutex_unlock(&dev->alu_mutex);
648 struct ksz_device *dev = ds->priv;
653 mutex_lock(&dev->alu_mutex);
658 ksz_write32(dev, REG_SW_ALU_INDEX_0, data);
662 ksz_write32(dev, REG_SW_ALU_INDEX_1, data);
665 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_READ | ALU_START);
668 ret = ksz9477_wait_alu_ready(dev);
670 dev_dbg(dev->dev, "Failed to read ALU\n");
674 ksz_read32(dev, REG_SW_ALU_VAL_A, &alu_table[0]);
676 ksz_read32(dev, REG_SW_ALU_VAL_B, &alu_table[1]);
677 ksz_read32(dev, REG_SW_ALU_VAL_C, &alu_table[2]);
678 ksz_read32(dev, REG_SW_ALU_VAL_D, &alu_table[3]);
697 ksz9477_write_table(dev, alu_table);
699 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_WRITE | ALU_START);
702 ret = ksz9477_wait_alu_ready(dev);
704 dev_dbg(dev->dev, "Failed to write ALU\n");
707 mutex_unlock(&dev->alu_mutex);
738 struct ksz_device *dev = ds->priv;
745 mutex_lock(&dev->alu_mutex);
748 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_START | ALU_SEARCH);
753 ksz_read32(dev, REG_SW_ALU_CTRL__4, &ksz_data);
760 dev_dbg(dev->dev, "Failed to search ALU\n");
769 ksz9477_read_table(dev, alu_table);
783 ksz_write32(dev, REG_SW_ALU_CTRL__4, 0);
785 mutex_unlock(&dev->alu_mutex);
793 struct ksz_device *dev = ds->priv;
803 mutex_lock(&dev->alu_mutex);
805 for (index = 0; index < dev->num_statics; index++) {
809 ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data);
812 if (ksz9477_wait_alu_sta_ready(dev)) {
813 dev_dbg(dev->dev, "Failed to read ALU STATIC\n");
818 ksz9477_read_table(dev, static_table);
835 if (index == dev->num_statics)
847 ksz9477_write_table(dev, static_table);
850 ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data);
853 if (ksz9477_wait_alu_sta_ready(dev))
854 dev_dbg(dev->dev, "Failed to read ALU STATIC\n");
857 mutex_unlock(&dev->alu_mutex);
863 struct ksz_device *dev = ds->priv;
874 mutex_lock(&dev->alu_mutex);
876 for (index = 0; index < dev->num_statics; index++) {
880 ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data);
883 ret = ksz9477_wait_alu_sta_ready(dev);
885 dev_dbg(dev->dev, "Failed to read ALU STATIC\n");
890 ksz9477_read_table(dev, static_table);
905 if (index == dev->num_statics)
919 ksz9477_write_table(dev, static_table);
922 ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data);
925 ret = ksz9477_wait_alu_sta_ready(dev);
927 dev_dbg(dev->dev, "Failed to read ALU STATIC\n");
930 mutex_unlock(&dev->alu_mutex);
939 struct ksz_device *dev = ds->priv;
942 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_RX, true);
944 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_TX, true);
946 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_SNIFFER, false);
949 ksz_port_cfg(dev, mirror->to_local_port, P_MIRROR_CTRL,
952 ksz_cfg(dev, S_MIRROR_CTRL, SW_MIRROR_RX_TX, false);
960 struct ksz_device *dev = ds->priv;
964 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_RX, false);
966 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_TX, false);
968 ksz_pread8(dev, port, P_MIRROR_CTRL, &data);
971 ksz_port_cfg(dev, mirror->to_local_port, P_MIRROR_CTRL,
975 static bool ksz9477_get_gbit(struct ksz_device *dev, u8 data)
979 if (dev->features & NEW_XMII)
986 static void ksz9477_set_gbit(struct ksz_device *dev, bool gbit, u8 *data)
988 if (dev->features & NEW_XMII) {
1001 static int ksz9477_get_xmii(struct ksz_device *dev, u8 data)
1005 if (dev->features & NEW_XMII) {
1037 static void ksz9477_set_xmii(struct ksz_device *dev, int mode, u8 *data)
1041 if (dev->features & NEW_XMII) {
1076 static phy_interface_t ksz9477_get_interface(struct ksz_device *dev, int port)
1083 if (port < dev->phy_port_cnt)
1085 ksz_pread8(dev, port, REG_PORT_XMII_CTRL_1, &data8);
1086 gbit = ksz9477_get_gbit(dev, data8);
1087 mode = ksz9477_get_xmii(dev, data8);
1114 static void ksz9477_port_mmd_write(struct ksz_device *dev, int port,
1117 ksz_pwrite16(dev, port, REG_PORT_PHY_MMD_SETUP,
1119 ksz_pwrite16(dev, port, REG_PORT_PHY_MMD_INDEX_DATA, reg_addr);
1120 ksz_pwrite16(dev, port, REG_PORT_PHY_MMD_SETUP,
1122 ksz_pwrite16(dev, port, REG_PORT_PHY_MMD_INDEX_DATA, val);
1125 static void ksz9477_phy_errata_setup(struct ksz_device *dev, int port)
1133 ksz9477_port_mmd_write(dev, port, 0x01, 0x6f, 0xdd0b);
1134 ksz9477_port_mmd_write(dev, port, 0x01, 0x8f, 0x6032);
1135 ksz9477_port_mmd_write(dev, port, 0x01, 0x9d, 0x248c);
1136 ksz9477_port_mmd_write(dev, port, 0x01, 0x75, 0x0060);
1137 ksz9477_port_mmd_write(dev, port, 0x01, 0xd3, 0x7777);
1138 ksz9477_port_mmd_write(dev, port, 0x1c, 0x06, 0x3008);
1139 ksz9477_port_mmd_write(dev, port, 0x1c, 0x08, 0x2001);
1144 ksz9477_port_mmd_write(dev, port, 0x1c, 0x04, 0x00d0);
1149 if (dev->features & GBIT_SUPPORT)
1150 ksz9477_port_mmd_write(dev, port, 0x07, 0x3c, 0x0000);
1155 ksz9477_port_mmd_write(dev, port, 0x1c, 0x13, 0x6eff);
1156 ksz9477_port_mmd_write(dev, port, 0x1c, 0x14, 0xe6ff);
1157 ksz9477_port_mmd_write(dev, port, 0x1c, 0x15, 0x6eff);
1158 ksz9477_port_mmd_write(dev, port, 0x1c, 0x16, 0xe6ff);
1159 ksz9477_port_mmd_write(dev, port, 0x1c, 0x17, 0x00ff);
1160 ksz9477_port_mmd_write(dev, port, 0x1c, 0x18, 0x43ff);
1161 ksz9477_port_mmd_write(dev, port, 0x1c, 0x19, 0xc3ff);
1162 ksz9477_port_mmd_write(dev, port, 0x1c, 0x1a, 0x6fff);
1163 ksz9477_port_mmd_write(dev, port, 0x1c, 0x1b, 0x07ff);
1164 ksz9477_port_mmd_write(dev, port, 0x1c, 0x1c, 0x0fff);
1165 ksz9477_port_mmd_write(dev, port, 0x1c, 0x1d, 0xe7ff);
1166 ksz9477_port_mmd_write(dev, port, 0x1c, 0x1e, 0xefff);
1167 ksz9477_port_mmd_write(dev, port, 0x1c, 0x20, 0xeeee);
1170 static void ksz9477_port_setup(struct ksz_device *dev, int port, bool cpu_port)
1175 struct ksz_port *p = &dev->ports[port];
1179 ksz_port_cfg(dev, port, REG_PORT_CTRL_0, PORT_TAIL_TAG_ENABLE,
1182 ksz_port_cfg(dev, port, REG_PORT_CTRL_0, PORT_MAC_LOOPBACK, false);
1185 ksz_port_cfg(dev, port, REG_PORT_MAC_CTRL_1, PORT_BACK_PRESSURE, true);
1188 ksz_port_cfg(dev, port, P_BCAST_STORM_CTRL, PORT_BROADCAST_STORM, true);
1191 ksz_port_cfg(dev, port, P_PRIO_CTRL, PORT_DIFFSERV_PRIO_ENABLE, false);
1194 ksz_port_cfg(dev, port, REG_PORT_MRI_MAC_CTRL, PORT_USER_PRIO_CEILING,
1196 ksz9477_port_cfg32(dev, port, REG_PORT_MTI_QUEUE_CTRL_0__4,
1200 ksz_port_cfg(dev, port, P_PRIO_CTRL, PORT_802_1P_PRIO_ENABLE, true);
1202 if (port < dev->phy_port_cnt) {
1204 ksz_port_cfg(dev, port, REG_PORT_CTRL_0,
1208 if (dev->phy_errata_9477)
1209 ksz9477_phy_errata_setup(dev, port);
1212 ksz_port_cfg(dev, port, REG_PORT_CTRL_0,
1217 ksz_pread8(dev, port, REG_PORT_XMII_CTRL_1, &data8);
1220 ksz9477_set_xmii(dev, 0, &data8);
1221 ksz9477_set_gbit(dev, false, &data8);
1225 ksz9477_set_xmii(dev, 1, &data8);
1226 ksz9477_set_gbit(dev, false, &data8);
1230 ksz9477_set_xmii(dev, 2, &data8);
1231 ksz9477_set_gbit(dev, true, &data8);
1235 ksz9477_set_xmii(dev, 3, &data8);
1236 ksz9477_set_gbit(dev, true, &data8);
1246 if (dev->features & IS_9893)
1251 ksz_pwrite8(dev, port, REG_PORT_XMII_CTRL_1, data8);
1254 mutex_lock(&dev->dev_mutex);
1256 member = dev->port_mask;
1258 member = dev->host_mask | p->vid_member;
1259 mutex_unlock(&dev->dev_mutex);
1260 ksz9477_cfg_port_member(dev, port, member);
1263 if (port < dev->phy_port_cnt)
1264 ksz_pread16(dev, port, REG_PORT_PHY_INT_ENABLE, &data16);
1269 struct ksz_device *dev = ds->priv;
1273 ds->num_ports = dev->port_cnt;
1275 for (i = 0; i < dev->port_cnt; i++) {
1276 if (dsa_is_cpu_port(ds, i) && (dev->cpu_ports & (1 << i))) {
1281 dev->cpu_port = i;
1282 dev->host_mask = (1 << dev->cpu_port);
1283 dev->port_mask |= dev->host_mask;
1284 p = &dev->ports[i];
1290 interface = ksz9477_get_interface(dev, i);
1292 if (dev->compat_interface) {
1293 dev_warn(dev->dev,
1297 p->interface = dev->compat_interface;
1309 dev_info(dev->dev,
1317 ksz9477_port_setup(dev, i, true);
1318 p->vid_member = dev->port_mask;
1323 dev->member = dev->host_mask;
1325 for (i = 0; i < dev->mib_port_cnt; i++) {
1326 if (i == dev->cpu_port)
1328 p = &dev->ports[i];
1334 p->member = dev->port_mask;
1337 if (i < dev->phy_port_cnt)
1339 if (dev->chip_id == 0x00947700 && i == 6) {
1350 struct ksz_device *dev = ds->priv;
1353 dev->vlan_cache = devm_kcalloc(dev->dev, sizeof(struct vlan_table),
1354 dev->num_vlans, GFP_KERNEL);
1355 if (!dev->vlan_cache)
1358 ret = ksz9477_reset_switch(dev);
1360 dev_err(ds->dev, "failed to reset switch\n");
1365 ksz9477_cfg32(dev, REG_SW_QM_CTRL__4, UNICAST_VLAN_BOUNDARY,
1369 ksz_cfg(dev, REG_SW_MAC_CTRL_0, SW_CHECK_LENGTH, false);
1372 ksz_cfg(dev, REG_SW_MAC_CTRL_1, SW_LEGAL_PACKET_DISABLE, true);
1376 ksz_cfg(dev, REG_SW_MAC_CTRL_1, MULTICAST_STORM_DISABLE, true);
1379 ksz_cfg(dev, REG_SW_MAC_CTRL_5, SW_OUT_RATE_LIMIT_QUEUE_BASED, true);
1382 ksz_cfg(dev, REG_SW_MAC_CTRL_6, SW_MIB_COUNTER_FREEZE, true);
1385 ksz_cfg(dev, REG_SW_OPERATION, SW_START, true);
1387 ksz_init_mib_timer(dev);
1425 static int ksz9477_switch_detect(struct ksz_device *dev)
1434 ret = ksz_read8(dev, REG_SW_GLOBAL_SERIAL_CTRL_0, &data8);
1439 ret = ksz_write8(dev, REG_SW_GLOBAL_SERIAL_CTRL_0, data8);
1444 ret = ksz_read32(dev, REG_CHIP_ID0__1, &id32);
1447 ret = ksz_read8(dev, REG_GLOBAL_OPTIONS, &data8);
1452 dev->mib_port_cnt = TOTAL_PORT_NUM;
1453 dev->phy_port_cnt = 5;
1456 dev->features = GBIT_SUPPORT;
1458 dev_dbg(dev->dev, "Switch detect: ID=%08x%02x\n", id32, data8);
1463 dev_info(dev->dev, "Found KSZ9893\n");
1464 dev->features |= IS_9893;
1468 dev->features &= ~GBIT_SUPPORT;
1469 dev->mib_port_cnt = 3;
1470 dev->phy_port_cnt = 2;
1472 dev_info(dev->dev, "Found KSZ9477 or compatible\n");
1474 dev->features |= NEW_XMII;
1478 dev->features &= ~GBIT_SUPPORT;
1484 dev->chip_id = id32;
1542 static int ksz9477_switch_init(struct ksz_device *dev)
1546 dev->ds->ops = &ksz9477_switch_ops;
1551 if (dev->chip_id == chip->chip_id) {
1552 dev->name = chip->dev_name;
1553 dev->num_vlans = chip->num_vlans;
1554 dev->num_alus = chip->num_alus;
1555 dev->num_statics = chip->num_statics;
1556 dev->port_cnt = chip->port_cnt;
1557 dev->cpu_ports = chip->cpu_ports;
1558 dev->phy_errata_9477 = chip->phy_errata_9477;
1565 if (!dev->port_cnt)
1568 dev->port_mask = (1 << dev->port_cnt) - 1;
1570 dev->reg_mib_cnt = SWITCH_COUNTER_NUM;
1571 dev->mib_cnt = TOTAL_SWITCH_COUNTER_NUM;
1573 i = dev->mib_port_cnt;
1574 dev->ports = devm_kzalloc(dev->dev, sizeof(struct ksz_port) * i,
1576 if (!dev->ports)
1578 for (i = 0; i < dev->mib_port_cnt; i++) {
1579 mutex_init(&dev->ports[i].mib.cnt_mutex);
1580 dev->ports[i].mib.counters =
1581 devm_kzalloc(dev->dev,
1585 if (!dev->ports[i].mib.counters)
1590 dev->ds->num_ports = dev->port_cnt;
1595 static void ksz9477_switch_exit(struct ksz_device *dev)
1597 ksz9477_reset_switch(dev);
1615 int ksz9477_switch_register(struct ksz_device *dev)
1620 ret = ksz_switch_register(dev, &ksz9477_dev_ops);
1624 for (i = 0; i < dev->phy_port_cnt; ++i) {
1625 if (!dsa_is_user_port(dev->ds, i))
1628 phydev = dsa_to_port(dev->ds, i)->slave->phydev;
1635 if (!(dev->features & GBIT_SUPPORT))