Lines Matching refs:pcie
333 static int kvaser_pciefd_spi_wait_loop(struct kvaser_pciefd *pcie, int msk)
338 ret = readl_poll_timeout(pcie->reg_base + KVASER_PCIEFD_SPI_STATUS_REG,
344 static int kvaser_pciefd_spi_cmd(struct kvaser_pciefd *pcie, const u8 *tx,
349 iowrite32(BIT(0), pcie->reg_base + KVASER_PCIEFD_SPI_SSEL_REG);
350 iowrite32(BIT(10), pcie->reg_base + KVASER_PCIEFD_SPI_CTRL_REG);
351 ioread32(pcie->reg_base + KVASER_PCIEFD_SPI_RX_REG);
355 if (kvaser_pciefd_spi_wait_loop(pcie, KVASER_PCIEFD_SPI_TRDY))
358 iowrite32(*tx++, pcie->reg_base + KVASER_PCIEFD_SPI_TX_REG);
360 if (kvaser_pciefd_spi_wait_loop(pcie, KVASER_PCIEFD_SPI_RRDY))
363 ioread32(pcie->reg_base + KVASER_PCIEFD_SPI_RX_REG);
368 if (kvaser_pciefd_spi_wait_loop(pcie, KVASER_PCIEFD_SPI_TRDY))
371 iowrite32(0, pcie->reg_base + KVASER_PCIEFD_SPI_TX_REG);
373 if (kvaser_pciefd_spi_wait_loop(pcie, KVASER_PCIEFD_SPI_RRDY))
376 *rx++ = ioread32(pcie->reg_base + KVASER_PCIEFD_SPI_RX_REG);
379 if (kvaser_pciefd_spi_wait_loop(pcie, KVASER_PCIEFD_SPI_TMT))
382 iowrite32(0, pcie->reg_base + KVASER_PCIEFD_SPI_CTRL_REG);
385 dev_err(&pcie->pci->dev, "Flash SPI transfer failed\n");
392 static int kvaser_pciefd_cfg_read_and_verify(struct kvaser_pciefd *pcie,
406 res = kvaser_pciefd_spi_cmd(pcie, cmd, ARRAY_SIZE(cmd), (u8 *)img,
414 dev_err(&pcie->pci->dev,
420 dev_err(&pcie->pci->dev,
427 dev_err(&pcie->pci->dev,
435 static void kvaser_pciefd_cfg_read_params(struct kvaser_pciefd *pcie,
441 memcpy(&pcie->nr_channels, param->data, le32_to_cpu(param->len));
444 static int kvaser_pciefd_read_cfg(struct kvaser_pciefd *pcie)
452 res = kvaser_pciefd_spi_cmd(pcie, cmd, ARRAY_SIZE(cmd), cmd, 1);
461 dev_err(&pcie->pci->dev,
470 res = kvaser_pciefd_spi_cmd(pcie, cmd, 1, cmd, 1);
476 dev_err(&pcie->pci->dev, "Unexpected WIP bit set in flash\n");
480 res = kvaser_pciefd_cfg_read_and_verify(pcie, img);
486 kvaser_pciefd_cfg_read_params(pcie, img);
934 static int kvaser_pciefd_setup_can_ctrls(struct kvaser_pciefd *pcie)
938 for (i = 0; i < pcie->nr_channels; i++) {
950 can->reg_base = pcie->reg_base + KVASER_PCIEFD_KCAN0_BASE +
953 can->kv_pcie = pcie;
971 dev_err(&pcie->pci->dev,
978 can->can.clock.freq = pcie->freq;
999 dev_err(&pcie->pci->dev,
1011 SET_NETDEV_DEV(netdev, &pcie->pci->dev);
1017 pcie->can[i] = can;
1024 static int kvaser_pciefd_reg_candev(struct kvaser_pciefd *pcie)
1028 for (i = 0; i < pcie->nr_channels; i++) {
1029 int err = register_candev(pcie->can[i]->can.dev);
1036 unregister_candev(pcie->can[j]->can.dev);
1044 static void kvaser_pciefd_write_dma_map(struct kvaser_pciefd *pcie,
1056 iowrite32(word1, pcie->reg_base + offset);
1057 iowrite32(word2, pcie->reg_base + offset + 4);
1060 static int kvaser_pciefd_setup_dma(struct kvaser_pciefd *pcie)
1068 iowrite32(0, pcie->reg_base + KVASER_PCIEFD_SRB_CTRL_REG);
1072 pcie->dma_data[i] =
1073 dmam_alloc_coherent(&pcie->pci->dev,
1078 if (!pcie->dma_data[i] || !dma_addr[i]) {
1079 dev_err(&pcie->pci->dev, "Rx dma_alloc(%u) failure\n",
1084 kvaser_pciefd_write_dma_map(pcie, dma_addr[i], offset);
1090 pcie->reg_base + KVASER_PCIEFD_SRB_CMD_REG);
1093 srb_packet_count = ioread32(pcie->reg_base + KVASER_PCIEFD_SRB_RX_NR_PACKETS_REG) &
1097 ioread32(pcie->reg_base + KVASER_PCIEFD_SRB_FIFO_LAST_REG);
1101 srb_status = ioread32(pcie->reg_base + KVASER_PCIEFD_SRB_STAT_REG);
1103 dev_err(&pcie->pci->dev, "DMA not idle before enabling\n");
1109 pcie->reg_base + KVASER_PCIEFD_SRB_CTRL_REG);
1114 static int kvaser_pciefd_setup_board(struct kvaser_pciefd *pcie)
1120 ret = kvaser_pciefd_read_cfg(pcie);
1124 sysid = ioread32(pcie->reg_base + KVASER_PCIEFD_SYSID_VERSION_REG);
1126 if (pcie->nr_channels != sysid_nr_chan) {
1127 dev_err(&pcie->pci->dev,
1129 pcie->nr_channels,
1134 if (pcie->nr_channels > KVASER_PCIEFD_MAX_CAN_CHANNELS)
1135 pcie->nr_channels = KVASER_PCIEFD_MAX_CAN_CHANNELS;
1137 build = ioread32(pcie->reg_base + KVASER_PCIEFD_SYSID_BUILD_REG);
1138 dev_dbg(&pcie->pci->dev, "Version %u.%u.%u\n",
1143 srb_status = ioread32(pcie->reg_base + KVASER_PCIEFD_SRB_STAT_REG);
1145 dev_err(&pcie->pci->dev,
1150 pcie->bus_freq = ioread32(pcie->reg_base +
1152 pcie->freq = ioread32(pcie->reg_base + KVASER_PCIEFD_SYSID_CANFREQ_REG);
1153 pcie->freq_to_ticks_div = pcie->freq / 1000000;
1154 if (pcie->freq_to_ticks_div == 0)
1155 pcie->freq_to_ticks_div = 1;
1158 iowrite32(0, pcie->reg_base + KVASER_PCIEFD_LOOP_REG);
1162 static int kvaser_pciefd_handle_data_packet(struct kvaser_pciefd *pcie,
1173 if (ch_id >= pcie->nr_channels)
1176 priv = &pcie->can[ch_id]->can;
1214 pcie->freq_to_ticks_div));
1337 static int kvaser_pciefd_handle_error_packet(struct kvaser_pciefd *pcie,
1343 if (ch_id >= pcie->nr_channels)
1346 can = pcie->can[ch_id];
1414 static int kvaser_pciefd_handle_status_packet(struct kvaser_pciefd *pcie,
1422 if (ch_id >= pcie->nr_channels)
1425 can = pcie->can[ch_id];
1473 static int kvaser_pciefd_handle_eack_packet(struct kvaser_pciefd *pcie,
1479 if (ch_id >= pcie->nr_channels)
1482 can = pcie->can[ch_id];
1536 static int kvaser_pciefd_handle_ack_packet(struct kvaser_pciefd *pcie,
1543 if (ch_id >= pcie->nr_channels)
1546 can = pcie->can[ch_id];
1579 static int kvaser_pciefd_handle_eflush_packet(struct kvaser_pciefd *pcie,
1585 if (ch_id >= pcie->nr_channels)
1588 can = pcie->can[ch_id];
1596 static int kvaser_pciefd_read_packet(struct kvaser_pciefd *pcie, int *start_pos,
1599 __le32 *buffer = pcie->dma_data[dma_buf];
1625 ret = kvaser_pciefd_handle_data_packet(pcie, p, &buffer[pos]);
1636 ret = kvaser_pciefd_handle_ack_packet(pcie, p);
1640 ret = kvaser_pciefd_handle_status_packet(pcie, p);
1644 ret = kvaser_pciefd_handle_error_packet(pcie, p);
1648 ret = kvaser_pciefd_handle_eack_packet(pcie, p);
1652 ret = kvaser_pciefd_handle_eflush_packet(pcie, p);
1658 dev_info(&pcie->pci->dev,
1663 dev_err(&pcie->pci->dev, "Unknown packet type 0x%08X\n", type);
1683 static int kvaser_pciefd_read_buffer(struct kvaser_pciefd *pcie, int dma_buf)
1689 res = kvaser_pciefd_read_packet(pcie, &pos, dma_buf);
1695 static int kvaser_pciefd_receive_irq(struct kvaser_pciefd *pcie)
1699 irq = ioread32(pcie->reg_base + KVASER_PCIEFD_SRB_IRQ_REG);
1701 kvaser_pciefd_read_buffer(pcie, 0);
1704 pcie->reg_base + KVASER_PCIEFD_SRB_CMD_REG);
1708 kvaser_pciefd_read_buffer(pcie, 1);
1711 pcie->reg_base + KVASER_PCIEFD_SRB_CMD_REG);
1718 dev_err(&pcie->pci->dev, "DMA IRQ error 0x%08X\n", irq);
1720 iowrite32(irq, pcie->reg_base + KVASER_PCIEFD_SRB_IRQ_REG);
1747 struct kvaser_pciefd *pcie = (struct kvaser_pciefd *)dev;
1751 board_irq = ioread32(pcie->reg_base + KVASER_PCIEFD_IRQ_REG);
1757 kvaser_pciefd_receive_irq(pcie);
1759 for (i = 0; i < pcie->nr_channels; i++) {
1760 if (!pcie->can[i]) {
1761 dev_err(&pcie->pci->dev,
1768 kvaser_pciefd_transmit_irq(pcie->can[i]);
1771 iowrite32(board_irq, pcie->reg_base + KVASER_PCIEFD_IRQ_REG);
1775 static void kvaser_pciefd_teardown_can_ctrls(struct kvaser_pciefd *pcie)
1780 for (i = 0; i < pcie->nr_channels; i++) {
1781 can = pcie->can[i];
1795 struct kvaser_pciefd *pcie;
1797 pcie = devm_kzalloc(&pdev->dev, sizeof(*pcie), GFP_KERNEL);
1798 if (!pcie)
1801 pci_set_drvdata(pdev, pcie);
1802 pcie->pci = pdev;
1812 pcie->reg_base = pci_iomap(pdev, 0, 0);
1813 if (!pcie->reg_base) {
1818 err = kvaser_pciefd_setup_board(pcie);
1822 err = kvaser_pciefd_setup_dma(pcie);
1828 err = kvaser_pciefd_setup_can_ctrls(pcie);
1832 err = request_irq(pcie->pci->irq, kvaser_pciefd_irq_handler,
1833 IRQF_SHARED, KVASER_PCIEFD_DRV_NAME, pcie);
1838 pcie->reg_base + KVASER_PCIEFD_SRB_IRQ_REG);
1843 pcie->reg_base + KVASER_PCIEFD_SRB_IEN_REG);
1847 pcie->reg_base + KVASER_PCIEFD_IRQ_REG);
1849 pcie->reg_base + KVASER_PCIEFD_IEN_REG);
1853 pcie->reg_base + KVASER_PCIEFD_SRB_CMD_REG);
1855 pcie->reg_base + KVASER_PCIEFD_SRB_CMD_REG);
1857 err = kvaser_pciefd_reg_candev(pcie);
1865 iowrite32(0, pcie->reg_base + KVASER_PCIEFD_IEN_REG);
1866 free_irq(pcie->pci->irq, pcie);
1869 kvaser_pciefd_teardown_can_ctrls(pcie);
1870 iowrite32(0, pcie->reg_base + KVASER_PCIEFD_SRB_CTRL_REG);
1874 pci_iounmap(pdev, pcie->reg_base);
1885 static void kvaser_pciefd_remove_all_ctrls(struct kvaser_pciefd *pcie)
1890 for (i = 0; i < pcie->nr_channels; i++) {
1891 can = pcie->can[i];
1905 struct kvaser_pciefd *pcie = pci_get_drvdata(pdev);
1907 kvaser_pciefd_remove_all_ctrls(pcie);
1910 iowrite32(0, pcie->reg_base + KVASER_PCIEFD_SRB_CTRL_REG);
1912 pcie->reg_base + KVASER_PCIEFD_IRQ_REG);
1913 iowrite32(0, pcie->reg_base + KVASER_PCIEFD_IEN_REG);
1915 free_irq(pcie->pci->irq, pcie);
1918 pci_iounmap(pdev, pcie->reg_base);