Lines Matching defs:reg_base
264 void __iomem *reg_base;
277 void __iomem *reg_base;
338 ret = readl_poll_timeout(pcie->reg_base + KVASER_PCIEFD_SPI_STATUS_REG,
349 iowrite32(BIT(0), pcie->reg_base + KVASER_PCIEFD_SPI_SSEL_REG);
350 iowrite32(BIT(10), pcie->reg_base + KVASER_PCIEFD_SPI_CTRL_REG);
351 ioread32(pcie->reg_base + KVASER_PCIEFD_SPI_RX_REG);
358 iowrite32(*tx++, pcie->reg_base + KVASER_PCIEFD_SPI_TX_REG);
363 ioread32(pcie->reg_base + KVASER_PCIEFD_SPI_RX_REG);
371 iowrite32(0, pcie->reg_base + KVASER_PCIEFD_SPI_TX_REG);
376 *rx++ = ioread32(pcie->reg_base + KVASER_PCIEFD_SPI_RX_REG);
382 iowrite32(0, pcie->reg_base + KVASER_PCIEFD_SPI_CTRL_REG);
499 iowrite32(cmd, can->reg_base + KVASER_PCIEFD_KCAN_CMD_REG);
508 mode = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG);
511 iowrite32(mode, can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG);
522 mode = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG);
524 iowrite32(mode, can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG);
538 iowrite32(msk, can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG);
550 mode = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG);
572 iowrite32(mode, can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG);
583 iowrite32(-1, can->reg_base + KVASER_PCIEFD_KCAN_IRQ_REG);
585 can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG);
587 status = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_STAT_REG);
594 iowrite32(cmd, can->reg_base + KVASER_PCIEFD_KCAN_CMD_REG);
599 mode = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG);
601 iowrite32(mode, can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG);
624 iowrite32(0, can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG);
625 iowrite32(-1, can->reg_base + KVASER_PCIEFD_KCAN_IRQ_REG);
628 can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG);
630 mode = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG);
632 iowrite32(mode, can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG);
641 iowrite32(0, can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG);
642 iowrite32(-1, can->reg_base + KVASER_PCIEFD_KCAN_IRQ_REG);
663 pwm_ctrl = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_PWM_REG);
668 iowrite32(pwm_ctrl, can->reg_base + KVASER_PCIEFD_KCAN_PWM_REG);
686 iowrite32(pwm_ctrl, can->reg_base + KVASER_PCIEFD_KCAN_PWM_REG);
692 iowrite32(pwm_ctrl, can->reg_base + KVASER_PCIEFD_KCAN_PWM_REG);
728 iowrite32(0, can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG);
800 can->reg_base + KVASER_PCIEFD_KCAN_FIFO_REG);
802 can->reg_base + KVASER_PCIEFD_KCAN_FIFO_REG);
808 iowrite32_rep(can->reg_base +
812 __raw_writel(data_last, can->reg_base +
816 __raw_writel(0, can->reg_base +
820 count = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_TX_NPACKETS_REG);
853 mode = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG);
857 can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG);
860 ret = readl_poll_timeout(can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG,
870 iowrite32(btrn, can->reg_base + KVASER_PCIEFD_KCAN_BTRD_REG);
872 iowrite32(btrn, can->reg_base + KVASER_PCIEFD_KCAN_BTRN_REG);
875 iowrite32(mode, can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG);
950 can->reg_base = pcie->reg_base + KVASER_PCIEFD_KCAN0_BASE +
965 iowrite32(0, can->reg_base + KVASER_PCIEFD_KCAN_BUS_LOAD_REG);
967 tx_npackets = ioread32(can->reg_base +
997 status = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_STAT_REG);
1013 iowrite32(-1, can->reg_base + KVASER_PCIEFD_KCAN_IRQ_REG);
1015 can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG);
1056 iowrite32(word1, pcie->reg_base + offset);
1057 iowrite32(word2, pcie->reg_base + offset + 4);
1068 iowrite32(0, pcie->reg_base + KVASER_PCIEFD_SRB_CTRL_REG);
1090 pcie->reg_base + KVASER_PCIEFD_SRB_CMD_REG);
1093 srb_packet_count = ioread32(pcie->reg_base + KVASER_PCIEFD_SRB_RX_NR_PACKETS_REG) &
1097 ioread32(pcie->reg_base + KVASER_PCIEFD_SRB_FIFO_LAST_REG);
1101 srb_status = ioread32(pcie->reg_base + KVASER_PCIEFD_SRB_STAT_REG);
1109 pcie->reg_base + KVASER_PCIEFD_SRB_CTRL_REG);
1124 sysid = ioread32(pcie->reg_base + KVASER_PCIEFD_SYSID_VERSION_REG);
1137 build = ioread32(pcie->reg_base + KVASER_PCIEFD_SYSID_BUILD_REG);
1143 srb_status = ioread32(pcie->reg_base + KVASER_PCIEFD_SRB_STAT_REG);
1150 pcie->bus_freq = ioread32(pcie->reg_base +
1152 pcie->freq = ioread32(pcie->reg_base + KVASER_PCIEFD_SYSID_CANFREQ_REG);
1158 iowrite32(0, pcie->reg_base + KVASER_PCIEFD_LOOP_REG);
1427 status = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_STAT_REG);
1439 can->reg_base + KVASER_PCIEFD_KCAN_IRQ_REG);
1442 iowrite32(cmd, can->reg_base + KVASER_PCIEFD_KCAN_CMD_REG);
1448 u8 count = ioread32(can->reg_base +
1453 can->reg_base + KVASER_PCIEFD_KCAN_CTRL_REG);
1486 u8 count = ioread32(can->reg_base +
1491 can->reg_base + KVASER_PCIEFD_KCAN_CTRL_REG);
1561 u8 count = ioread32(can->reg_base +
1699 irq = ioread32(pcie->reg_base + KVASER_PCIEFD_SRB_IRQ_REG);
1704 pcie->reg_base + KVASER_PCIEFD_SRB_CMD_REG);
1711 pcie->reg_base + KVASER_PCIEFD_SRB_CMD_REG);
1720 iowrite32(irq, pcie->reg_base + KVASER_PCIEFD_SRB_IRQ_REG);
1726 u32 irq = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_IRQ_REG);
1741 iowrite32(irq, can->reg_base + KVASER_PCIEFD_KCAN_IRQ_REG);
1751 board_irq = ioread32(pcie->reg_base + KVASER_PCIEFD_IRQ_REG);
1771 iowrite32(board_irq, pcie->reg_base + KVASER_PCIEFD_IRQ_REG);
1784 can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG);
1812 pcie->reg_base = pci_iomap(pdev, 0, 0);
1813 if (!pcie->reg_base) {
1838 pcie->reg_base + KVASER_PCIEFD_SRB_IRQ_REG);
1843 pcie->reg_base + KVASER_PCIEFD_SRB_IEN_REG);
1847 pcie->reg_base + KVASER_PCIEFD_IRQ_REG);
1849 pcie->reg_base + KVASER_PCIEFD_IEN_REG);
1853 pcie->reg_base + KVASER_PCIEFD_SRB_CMD_REG);
1855 pcie->reg_base + KVASER_PCIEFD_SRB_CMD_REG);
1865 iowrite32(0, pcie->reg_base + KVASER_PCIEFD_IEN_REG);
1870 iowrite32(0, pcie->reg_base + KVASER_PCIEFD_SRB_CTRL_REG);
1874 pci_iounmap(pdev, pcie->reg_base);
1894 can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG);
1910 iowrite32(0, pcie->reg_base + KVASER_PCIEFD_SRB_CTRL_REG);
1912 pcie->reg_base + KVASER_PCIEFD_IRQ_REG);
1913 iowrite32(0, pcie->reg_base + KVASER_PCIEFD_IEN_REG);
1918 pci_iounmap(pdev, pcie->reg_base);