Lines Matching refs:reg_ctrl
584 u32 reg_ctrl = (priv->reg_ctrl_default | FLEXCAN_CTRL_ERR_MSK);
586 priv->write(reg_ctrl, ®s->ctrl);
592 u32 reg_ctrl = (priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_MSK);
594 priv->write(reg_ctrl, ®s->ctrl);
954 u32 reg_ctrl, reg_id, reg_iflag1;
963 reg_ctrl = priv->read(&mb->can_ctrl);
964 } while (reg_ctrl & FLEXCAN_MB_CODE_RX_BUSY_BIT);
967 code = reg_ctrl & FLEXCAN_MB_CODE_MASK;
982 reg_ctrl = priv->read(&mb->can_ctrl);
990 if (reg_ctrl & FLEXCAN_MB_CNT_EDL)
1000 *timestamp = reg_ctrl << 16;
1003 if (reg_ctrl & FLEXCAN_MB_CNT_IDE)
1008 if (reg_ctrl & FLEXCAN_MB_CNT_EDL) {
1009 cfd->len = can_dlc2len(get_canfd_dlc((reg_ctrl >> 16) & 0xf));
1011 if (reg_ctrl & FLEXCAN_MB_CNT_BRS)
1014 cfd->len = get_can_dlc((reg_ctrl >> 16) & 0xf);
1016 if (reg_ctrl & FLEXCAN_MB_CNT_RTR)
1020 if (reg_ctrl & FLEXCAN_MB_CNT_ESI)
1089 u32 reg_ctrl = priv->read(&priv->tx_mb->can_ctrl);
1093 0, reg_ctrl << 16);
1364 u32 reg_mcr, reg_ctrl, reg_ctrl2, reg_mecr;
1450 reg_ctrl = priv->read(®s->ctrl);
1451 reg_ctrl &= ~FLEXCAN_CTRL_TSYN;
1452 reg_ctrl |= FLEXCAN_CTRL_BOFF_REC | FLEXCAN_CTRL_LBUF |
1461 reg_ctrl |= FLEXCAN_CTRL_ERR_MSK;
1463 reg_ctrl &= ~FLEXCAN_CTRL_ERR_MSK;
1466 priv->reg_ctrl_default = reg_ctrl;
1468 reg_ctrl &= ~FLEXCAN_CTRL_ERR_ALL;
1469 netdev_dbg(dev, "%s: writing ctrl=0x%08x", __func__, reg_ctrl);
1470 priv->write(reg_ctrl, ®s->ctrl);