Lines Matching defs:ctrl
256 u32 ctrl; /* 0x04 - Not affected by Soft Reset */
586 priv->write(reg_ctrl, ®s->ctrl);
594 priv->write(reg_ctrl, ®s->ctrl);
755 u32 ctrl = FLEXCAN_MB_CODE_TX_DATA | ((can_len2dlc(cfd->len)) << 16);
765 ctrl |= FLEXCAN_MB_CNT_IDE | FLEXCAN_MB_CNT_SRR;
771 ctrl |= FLEXCAN_MB_CNT_RTR;
774 ctrl |= FLEXCAN_MB_CNT_EDL;
777 ctrl |= FLEXCAN_MB_CNT_BRS;
788 priv->write(ctrl, &priv->tx_mb->can_ctrl);
1171 reg = priv->read(®s->ctrl);
1184 netdev_dbg(dev, "writing ctrl=0x%08x\n", reg);
1185 priv->write(reg, ®s->ctrl);
1188 netdev_dbg(dev, "%s: mcr=0x%08x ctrl=0x%08x\n", __func__,
1189 priv->read(®s->mcr), priv->read(®s->ctrl));
1291 netdev_dbg(dev, "%s: mcr=0x%08x ctrl=0x%08x ctrl2=0x%08x fdctrl=0x%08x cbt=0x%08x fdcbt=0x%08x\n",
1293 priv->read(®s->mcr), priv->read(®s->ctrl),
1304 reg = priv->read(®s->ctrl);
1315 netdev_dbg(dev, "writing ctrl=0x%08x\n", reg);
1316 priv->write(reg, ®s->ctrl);
1450 reg_ctrl = priv->read(®s->ctrl);
1469 netdev_dbg(dev, "%s: writing ctrl=0x%08x", __func__, reg_ctrl);
1470 priv->write(reg_ctrl, ®s->ctrl);
1587 priv->write(priv->reg_ctrl_default, ®s->ctrl);
1594 netdev_dbg(dev, "%s: reading mcr=0x%08x ctrl=0x%08x\n", __func__,
1595 priv->read(®s->mcr), priv->read(®s->ctrl));
1626 ®s->ctrl);
1800 reg = priv->read(®s->ctrl);
1805 priv->write(reg, ®s->ctrl);