Lines Matching refs:controller
94 struct aspeed_smc_controller *controller;
106 struct mutex mutex; /* controller access mutex */
107 const struct aspeed_smc_info *info; /* type info of controller */
108 void __iomem *regs; /* controller registers */
197 #define SEGMENT_ADDR_REG(controller, cs) \
198 ((controller)->regs + SEGMENT_ADDR_REG0 + (cs) * 4)
258 return BIT(chip->controller->info->we0 + chip->cs);
263 struct aspeed_smc_controller *controller = chip->controller;
266 reg = readl(controller->regs + CONFIG_REG);
271 dev_dbg(controller->dev, "config write is not set ! @%p: 0x%08x\n",
272 controller->regs + CONFIG_REG, reg);
274 writel(reg, controller->regs + CONFIG_REG);
312 mutex_lock(&chip->controller->mutex);
320 mutex_unlock(&chip->controller->mutex);
402 static int aspeed_smc_unregister(struct aspeed_smc_controller *controller)
407 for (n = 0; n < controller->info->nce; n++) {
408 chip = controller->chips[n];
440 struct aspeed_smc_controller *controller = chip->controller;
444 if (controller->info->nce > 1) {
445 reg = readl(SEGMENT_ADDR_REG(controller, chip->cs));
453 return controller->ahb_base + offset;
456 static u32 aspeed_smc_ahb_base_phy(struct aspeed_smc_controller *controller)
458 u32 seg0_val = readl(SEGMENT_ADDR_REG(controller, 0));
466 struct aspeed_smc_controller *controller = chip->controller;
470 ahb_base_phy = aspeed_smc_ahb_base_phy(controller);
472 seg_reg = SEGMENT_ADDR_REG(controller, cs);
485 * controller.
487 if (start + size > ahb_base_phy + controller->ahb_window_size) {
488 size = ahb_base_phy + controller->ahb_window_size - start;
526 struct aspeed_smc_controller *controller = chip->controller;
531 * Each controller has a chip size limit for direct memory
534 if (size > controller->info->maxsize)
535 size = controller->info->maxsize;
538 * The AST2400 SPI controller only handles one chip and does
542 if (controller->info == &spi_2400_info)
546 * The AST2500 SPI controller has a HW bug when the CE0 chip
548 * prevent the controller from using bogus settings in the
551 if (chip->cs == 0 && controller->info == &spi_2500_info &&
559 ahb_base_phy = aspeed_smc_ahb_base_phy(controller);
567 u32 prev = readl(SEGMENT_ADDR_REG(controller, chip->cs - 1));
577 chip->ahb_base = controller->ahb_base + (start - ahb_base_phy);
584 if (chip->cs < controller->info->nce - 1)
598 struct aspeed_smc_controller *controller = chip->controller;
601 reg = readl(controller->regs + CONFIG_REG);
604 writel(reg, controller->regs + CONFIG_REG);
609 struct aspeed_smc_controller *controller = chip->controller;
614 reg = readl(controller->regs + CONFIG_REG);
617 writel(reg, controller->regs + CONFIG_REG);
621 * The first chip of the AST2500 FMC flash controller is strapped by
627 struct aspeed_smc_controller *controller = chip->controller;
630 reg = readl(controller->regs + CE_CONTROL_REG);
632 writel(reg, controller->regs + CE_CONTROL_REG);
636 * The AST2400 SPI flash controller does not have a CE Control
638 * controller level.
649 struct aspeed_smc_controller *controller = chip->controller;
650 const struct aspeed_smc_info *info = controller->info;
679 dev_dbg(controller->dev, "control register: %08x\n", reg);
683 dev_dbg(controller->dev,
701 dev_dbg(controller->dev, "default control register: %08x\n",
708 struct aspeed_smc_controller *controller = chip->controller;
709 const struct aspeed_smc_info *info = controller->info;
725 dev_dbg(controller->dev, "write control register: %08x\n",
730 * SPI NOR flags to adjust controller settings.
745 dev_dbg(controller->dev, "base control register: %08x\n",
759 static int aspeed_smc_setup_flash(struct aspeed_smc_controller *controller,
767 const struct aspeed_smc_info *info = controller->info;
768 struct device *dev = controller->dev;
795 if (controller->chips[cs]) {
797 cs, dev_name(controller->chips[cs]->nor.dev));
802 chip = devm_kzalloc(controller->dev, sizeof(*chip), GFP_KERNEL);
808 chip->controller = controller;
809 chip->ctl = controller->regs + info->ctl0 + cs * 4;
841 controller->chips[cs] = chip;
846 aspeed_smc_unregister(controller);
856 struct aspeed_smc_controller *controller;
867 controller = devm_kzalloc(&pdev->dev,
868 struct_size(controller, chips, info->nce),
870 if (!controller)
872 controller->info = info;
873 controller->dev = dev;
875 mutex_init(&controller->mutex);
876 platform_set_drvdata(pdev, controller);
879 controller->regs = devm_ioremap_resource(dev, res);
880 if (IS_ERR(controller->regs))
881 return PTR_ERR(controller->regs);
884 controller->ahb_base = devm_ioremap_resource(dev, res);
885 if (IS_ERR(controller->ahb_base))
886 return PTR_ERR(controller->ahb_base);
888 controller->ahb_window_size = resource_size(res);
890 ret = aspeed_smc_setup_flash(controller, np, res);