Lines Matching refs:tmio
30 #include <linux/mfd/tmio.h>
134 struct tmio_nand *tmio = mtd_to_tmio(nand_to_mtd(chip));
155 tmio_iowrite8(mode, tmio->fcr + FCR_MODE);
156 tmio->read_good = 0;
165 struct tmio_nand *tmio = mtd_to_tmio(nand_to_mtd(chip));
167 return !(tmio_ioread8(tmio->fcr + FCR_STATUS) & FCR_STATUS_BUSY);
172 struct tmio_nand *tmio = __tmio;
175 tmio_iowrite8(0x00, tmio->fcr + FCR_IMR);
176 complete(&tmio->comp);
189 struct tmio_nand *tmio = mtd_to_tmio(nand_to_mtd(nand_chip));
195 tmio_iowrite8(0x0f, tmio->fcr + FCR_ISR);
196 reinit_completion(&tmio->comp);
197 tmio_iowrite8(0x81, tmio->fcr + FCR_IMR);
200 timeout = wait_for_completion_timeout(&tmio->comp,
204 tmio_iowrite8(0x00, tmio->fcr + FCR_IMR);
205 dev_warn(&tmio->dev->dev, "still busy after 400 ms\n");
208 tmio_iowrite8(0x00, tmio->fcr + FCR_IMR);
209 dev_warn(&tmio->dev->dev, "timeout waiting for interrupt\n");
222 *tmio->read_good.
226 struct tmio_nand *tmio = mtd_to_tmio(nand_to_mtd(chip));
229 if (tmio->read_good--)
230 return tmio->read;
232 data = tmio_ioread16(tmio->fcr + FCR_DATA);
233 tmio->read = data >> 8;
246 struct tmio_nand *tmio = mtd_to_tmio(nand_to_mtd(chip));
248 tmio_iowrite16_rep(tmio->fcr + FCR_DATA, buf, len >> 1);
253 struct tmio_nand *tmio = mtd_to_tmio(nand_to_mtd(chip));
255 tmio_ioread16_rep(tmio->fcr + FCR_DATA, buf, len >> 1);
260 struct tmio_nand *tmio = mtd_to_tmio(nand_to_mtd(chip));
262 tmio_iowrite8(FCR_MODE_HWECC_RESET, tmio->fcr + FCR_MODE);
263 tmio_ioread8(tmio->fcr + FCR_DATA); /* dummy read */
264 tmio_iowrite8(FCR_MODE_HWECC_CALC, tmio->fcr + FCR_MODE);
270 struct tmio_nand *tmio = mtd_to_tmio(nand_to_mtd(chip));
273 tmio_iowrite8(FCR_MODE_HWECC_RESULT, tmio->fcr + FCR_MODE);
275 ecc = tmio_ioread16(tmio->fcr + FCR_DATA);
278 ecc = tmio_ioread16(tmio->fcr + FCR_DATA);
281 ecc = tmio_ioread16(tmio->fcr + FCR_DATA);
285 tmio_iowrite8(FCR_MODE_DATA, tmio->fcr + FCR_MODE);
306 static int tmio_hw_init(struct platform_device *dev, struct tmio_nand *tmio)
318 tmio_iowrite8(0x81, tmio->ccr + CCR_ICC);
321 tmio_iowrite16(tmio->fcr_base, tmio->ccr + CCR_BASE);
322 tmio_iowrite16(tmio->fcr_base >> 16, tmio->ccr + CCR_BASE + 2);
325 tmio_iowrite8(0x02, tmio->ccr + CCR_COMMAND);
329 tmio_iowrite8(0x02, tmio->ccr + CCR_NFPSC);
332 tmio_iowrite8(0x02, tmio->ccr + CCR_NFDC);
335 tmio_iowrite8(0x0f, tmio->fcr + FCR_ISR);
338 tmio_iowrite8(FCR_MODE_POWER_ON, tmio->fcr + FCR_MODE);
339 tmio_iowrite8(FCR_MODE_COMMAND, tmio->fcr + FCR_MODE);
340 tmio_iowrite8(NAND_CMD_RESET, tmio->fcr + FCR_DATA);
343 tmio_iowrite8(FCR_MODE_STANDBY, tmio->fcr + FCR_MODE);
350 static void tmio_hw_stop(struct platform_device *dev, struct tmio_nand *tmio)
354 tmio_iowrite8(FCR_MODE_POWER_OFF, tmio->fcr + FCR_MODE);
386 struct tmio_nand *tmio;
394 tmio = devm_kzalloc(&dev->dev, sizeof(*tmio), GFP_KERNEL);
395 if (!tmio)
398 init_completion(&tmio->comp);
400 tmio->dev = dev;
402 platform_set_drvdata(dev, tmio);
403 nand_chip = &tmio->chip;
405 mtd->name = "tmio-nand";
408 nand_controller_init(&tmio->controller);
409 tmio->controller.ops = &tmio_ops;
410 nand_chip->controller = &tmio->controller;
412 tmio->ccr = devm_ioremap(&dev->dev, ccr->start, resource_size(ccr));
413 if (!tmio->ccr)
416 tmio->fcr_base = fcr->start & 0xfffff;
417 tmio->fcr = devm_ioremap(&dev->dev, fcr->start, resource_size(fcr));
418 if (!tmio->fcr)
421 retval = tmio_hw_init(dev, tmio);
426 nand_chip->legacy.IO_ADDR_R = tmio->fcr;
427 nand_chip->legacy.IO_ADDR_W = tmio->fcr;
443 dev_name(&dev->dev), tmio);
449 tmio->irq = irq;
469 tmio_hw_stop(dev, tmio);
475 struct tmio_nand *tmio = platform_get_drvdata(dev);
476 struct nand_chip *chip = &tmio->chip;
482 tmio_hw_stop(dev, tmio);
518 .driver.name = "tmio-nand",
531 MODULE_ALIAS("platform:tmio-nand");