Lines Matching refs:ctrl
250 struct tegra_nand_controller *ctrl = data;
253 isr = readl_relaxed(ctrl->regs + ISR);
254 dma = readl_relaxed(ctrl->regs + DMA_MST_CTRL);
255 dev_dbg(ctrl->dev, "isr %08x\n", isr);
266 ctrl->last_read_error = true;
269 complete(&ctrl->command_complete);
272 dev_err(ctrl->dev, "FIFO underrun\n");
275 dev_err(ctrl->dev, "FIFO overrun\n");
279 writel_relaxed(dma, ctrl->regs + DMA_MST_CTRL);
280 complete(&ctrl->dma_complete);
284 writel_relaxed(isr, ctrl->regs + ISR);
308 static void tegra_nand_dump_reg(struct tegra_nand_controller *ctrl)
313 dev_err(ctrl->dev, "Tegra NAND controller register dump\n");
320 reg = readl_relaxed(ctrl->regs + (i * 4));
321 dev_err(ctrl->dev, "%s: 0x%08x\n", reg_name, reg);
325 static void tegra_nand_controller_abort(struct tegra_nand_controller *ctrl)
329 disable_irq(ctrl->irq);
332 writel_relaxed(0, ctrl->regs + DMA_MST_CTRL);
333 writel_relaxed(0, ctrl->regs + COMMAND);
336 isr = readl_relaxed(ctrl->regs + ISR);
337 writel_relaxed(isr, ctrl->regs + ISR);
338 dma = readl_relaxed(ctrl->regs + DMA_MST_CTRL);
339 writel_relaxed(dma, ctrl->regs + DMA_MST_CTRL);
341 reinit_completion(&ctrl->command_complete);
342 reinit_completion(&ctrl->dma_complete);
344 enable_irq(ctrl->irq);
352 struct tegra_nand_controller *ctrl = to_tegra_ctrl(chip->controller);
370 ctrl->regs + CMD_REG1);
374 ctrl->regs + CMD_REG2);
391 writel_relaxed(addr1, ctrl->regs + ADDR_REG1);
392 writel_relaxed(addr2, ctrl->regs + ADDR_REG2);
413 writel_relaxed(reg, ctrl->regs + RESP);
422 cmd |= COMMAND_GO | COMMAND_CE(ctrl->cur_cs);
423 writel_relaxed(cmd, ctrl->regs + COMMAND);
424 ret = wait_for_completion_timeout(&ctrl->command_complete,
427 dev_err(ctrl->dev, "COMMAND timeout\n");
428 tegra_nand_dump_reg(ctrl);
429 tegra_nand_controller_abort(ctrl);
434 reg = readl_relaxed(ctrl->regs + RESP);
461 struct tegra_nand_controller *ctrl = to_tegra_ctrl(chip->controller);
463 ctrl->cur_cs = nand->cs[die_nr];
477 static void tegra_nand_hw_ecc(struct tegra_nand_controller *ctrl,
483 writel_relaxed(nand->bch_config, ctrl->regs + BCH_CONFIG);
485 writel_relaxed(0, ctrl->regs + BCH_CONFIG);
488 writel_relaxed(nand->config_ecc, ctrl->regs + CONFIG);
490 writel_relaxed(nand->config, ctrl->regs + CONFIG);
497 struct tegra_nand_controller *ctrl = to_tegra_ctrl(chip->controller);
506 writel_relaxed(NAND_CMD_READ0, ctrl->regs + CMD_REG1);
507 writel_relaxed(NAND_CMD_READSTART, ctrl->regs + CMD_REG2);
509 writel_relaxed(NAND_CMD_SEQIN, ctrl->regs + CMD_REG1);
510 writel_relaxed(NAND_CMD_PAGEPROG, ctrl->regs + CMD_REG2);
519 writel_relaxed(addr1, ctrl->regs + ADDR_REG1);
522 writel_relaxed(page >> 16, ctrl->regs + ADDR_REG2);
529 dma_addr = dma_map_single(ctrl->dev, buf, mtd->writesize, dir);
530 ret = dma_mapping_error(ctrl->dev, dma_addr);
532 dev_err(ctrl->dev, "dma mapping error\n");
536 writel_relaxed(mtd->writesize - 1, ctrl->regs + DMA_CFG_A);
537 writel_relaxed(dma_addr, ctrl->regs + DATA_PTR);
541 dma_addr_oob = dma_map_single(ctrl->dev, oob_buf, mtd->oobsize,
543 ret = dma_mapping_error(ctrl->dev, dma_addr_oob);
545 dev_err(ctrl->dev, "dma mapping error\n");
550 writel_relaxed(oob_len - 1, ctrl->regs + DMA_CFG_B);
551 writel_relaxed(dma_addr_oob, ctrl->regs + TAG_PTR);
568 writel_relaxed(dma_ctrl, ctrl->regs + DMA_MST_CTRL);
571 COMMAND_CE(ctrl->cur_cs);
583 writel_relaxed(cmd, ctrl->regs + COMMAND);
585 ret = wait_for_completion_timeout(&ctrl->command_complete,
588 dev_err(ctrl->dev, "COMMAND timeout\n");
589 tegra_nand_dump_reg(ctrl);
590 tegra_nand_controller_abort(ctrl);
595 ret = wait_for_completion_timeout(&ctrl->dma_complete,
598 dev_err(ctrl->dev, "DMA timeout\n");
599 tegra_nand_dump_reg(ctrl);
600 tegra_nand_controller_abort(ctrl);
608 dma_unmap_single(ctrl->dev, dma_addr_oob, mtd->oobsize, dir);
611 dma_unmap_single(ctrl->dev, dma_addr, mtd->writesize, dir);
656 struct tegra_nand_controller *ctrl = to_tegra_ctrl(chip->controller);
663 tegra_nand_hw_ecc(ctrl, chip, true);
665 tegra_nand_hw_ecc(ctrl, chip, false);
670 if (!ctrl->last_read_error)
682 ctrl->last_read_error = false;
683 dec_stat = readl_relaxed(ctrl->regs + DEC_STAT_BUF);
766 struct tegra_nand_controller *ctrl = to_tegra_ctrl(chip->controller);
770 tegra_nand_hw_ecc(ctrl, chip, true);
773 tegra_nand_hw_ecc(ctrl, chip, false);
778 static void tegra_nand_setup_timing(struct tegra_nand_controller *ctrl,
785 unsigned int rate = clk_get_rate(ctrl->clk) / 1000000;
808 writel_relaxed(reg, ctrl->regs + TIMING_1);
813 writel_relaxed(reg, ctrl->regs + TIMING_2);
819 struct tegra_nand_controller *ctrl = to_tegra_ctrl(chip->controller);
829 tegra_nand_setup_timing(ctrl, timings);
913 struct tegra_nand_controller *ctrl = to_tegra_ctrl(chip->controller);
928 dev_err(ctrl->dev, "Unsupported step size %d\n",
951 dev_err(ctrl->dev, "BCH supports 2K or 4K page size only\n");
958 dev_err(ctrl->dev,
987 dev_err(ctrl->dev, "ECC strength %d not supported\n",
1010 dev_err(ctrl->dev, "ECC strength %d not supported\n",
1016 dev_err(ctrl->dev, "ECC algorithm not supported\n");
1020 dev_info(ctrl->dev, "Using %s with strength %d per 512 byte step\n",
1043 dev_err(ctrl->dev, "Unsupported writesize %d\n",
1053 writel_relaxed(nand->config, ctrl->regs + CONFIG);
1065 struct tegra_nand_controller *ctrl)
1111 chip->controller = &ctrl->controller;
1138 ctrl->chip = chip;
1146 struct tegra_nand_controller *ctrl;
1150 ctrl = devm_kzalloc(&pdev->dev, sizeof(*ctrl), GFP_KERNEL);
1151 if (!ctrl)
1154 ctrl->dev = &pdev->dev;
1155 nand_controller_init(&ctrl->controller);
1156 ctrl->controller.ops = &tegra_nand_controller_ops;
1159 ctrl->regs = devm_ioremap_resource(&pdev->dev, res);
1160 if (IS_ERR(ctrl->regs))
1161 return PTR_ERR(ctrl->regs);
1167 ctrl->clk = devm_clk_get(&pdev->dev, "nand");
1168 if (IS_ERR(ctrl->clk))
1169 return PTR_ERR(ctrl->clk);
1171 err = clk_prepare_enable(ctrl->clk);
1177 dev_err(ctrl->dev, "Failed to reset HW: %d\n", err);
1181 writel_relaxed(HWSTATUS_CMD_DEFAULT, ctrl->regs + HWSTATUS_CMD);
1182 writel_relaxed(HWSTATUS_MASK_DEFAULT, ctrl->regs + HWSTATUS_MASK);
1183 writel_relaxed(INT_MASK, ctrl->regs + IER);
1185 init_completion(&ctrl->command_complete);
1186 init_completion(&ctrl->dma_complete);
1188 ctrl->irq = platform_get_irq(pdev, 0);
1189 err = devm_request_irq(&pdev->dev, ctrl->irq, tegra_nand_irq, 0,
1190 dev_name(&pdev->dev), ctrl);
1192 dev_err(ctrl->dev, "Failed to get IRQ: %d\n", err);
1196 writel_relaxed(DMA_MST_CTRL_IS_DONE, ctrl->regs + DMA_MST_CTRL);
1198 err = tegra_nand_chips_init(ctrl->dev, ctrl);
1202 platform_set_drvdata(pdev, ctrl);
1207 clk_disable_unprepare(ctrl->clk);
1213 struct tegra_nand_controller *ctrl = platform_get_drvdata(pdev);
1214 struct nand_chip *chip = ctrl->chip;
1224 clk_disable_unprepare(ctrl->clk);