Lines Matching defs:nand
460 struct tegra_nand_chip *nand = to_tegra_chip(chip);
463 ctrl->cur_cs = nand->cs[die_nr];
480 struct tegra_nand_chip *nand = to_tegra_chip(chip);
483 writel_relaxed(nand->bch_config, ctrl->regs + BCH_CONFIG);
488 writel_relaxed(nand->config_ecc, ctrl->regs + CONFIG);
490 writel_relaxed(nand->config, ctrl->regs + CONFIG);
657 struct tegra_nand_chip *nand = to_tegra_chip(chip);
725 u8 *oob = chip->oob_poi + nand->ecc.offset +
916 struct tegra_nand_chip *nand = to_tegra_chip(chip);
941 nand->config |= CONFIG_BUS_WIDTH_16;
967 nand->config_ecc = CONFIG_PIPE_EN | CONFIG_SKIP_SPARE |
974 nand->config_ecc |= CONFIG_HW_ECC | CONFIG_ECC_SEL |
978 nand->config_ecc |= CONFIG_TVAL_4;
981 nand->config_ecc |= CONFIG_TVAL_6;
984 nand->config_ecc |= CONFIG_TVAL_8;
995 nand->bch_config = BCH_ENABLE;
998 nand->bch_config |= BCH_TVAL_4;
1001 nand->bch_config |= BCH_TVAL_8;
1004 nand->bch_config |= BCH_TVAL_14;
1007 nand->bch_config |= BCH_TVAL_16;
1028 nand->config |= CONFIG_PS_256;
1031 nand->config |= CONFIG_PS_512;
1034 nand->config |= CONFIG_PS_1024;
1037 nand->config |= CONFIG_PS_2048;
1040 nand->config |= CONFIG_PS_4096;
1049 nand->config_ecc |= nand->config;
1052 nand->config |= CONFIG_TAG_BYTE_SIZE(mtd->oobsize - 1);
1053 writel_relaxed(nand->config, ctrl->regs + CONFIG);
1070 struct tegra_nand_chip *nand;
1096 nand = devm_kzalloc(dev, sizeof(*nand), GFP_KERNEL);
1097 if (!nand)
1100 nand->cs[0] = cs;
1102 nand->wp_gpio = devm_gpiod_get_optional(dev, "wp", GPIOD_OUT_LOW);
1104 if (IS_ERR(nand->wp_gpio)) {
1105 ret = PTR_ERR(nand->wp_gpio);
1110 chip = &nand->chip;
1129 mtd_ooblayout_ecc(mtd, 0, &nand->ecc);
1163 rst = devm_reset_control_get(&pdev->dev, "nand");
1167 ctrl->clk = devm_clk_get(&pdev->dev, "nand");
1230 { .compatible = "nvidia,tegra20-nand" },
1237 .name = "tegra-nand",