Lines Matching refs:nfc
6 * https://github.com/yuq/sunxi-nfc-mtd
259 struct sunxi_nfc *nfc = dev_id;
260 u32 st = readl(nfc->regs + NFC_REG_ST);
261 u32 ien = readl(nfc->regs + NFC_REG_INT);
267 complete(&nfc->complete);
269 writel(st & NFC_INT_MASK, nfc->regs + NFC_REG_ST);
270 writel(~st & ien & NFC_INT_MASK, nfc->regs + NFC_REG_INT);
275 static int sunxi_nfc_wait_events(struct sunxi_nfc *nfc, u32 events,
287 init_completion(&nfc->complete);
289 writel(events, nfc->regs + NFC_REG_INT);
291 ret = wait_for_completion_timeout(&nfc->complete,
298 writel(0, nfc->regs + NFC_REG_INT);
302 ret = readl_poll_timeout(nfc->regs + NFC_REG_ST, status,
307 writel(events & NFC_INT_MASK, nfc->regs + NFC_REG_ST);
310 dev_err(nfc->dev, "wait interrupt timedout\n");
315 static int sunxi_nfc_wait_cmd_fifo_empty(struct sunxi_nfc *nfc)
320 ret = readl_poll_timeout(nfc->regs + NFC_REG_ST, status,
324 dev_err(nfc->dev, "wait for empty cmd FIFO timedout\n");
329 static int sunxi_nfc_rst(struct sunxi_nfc *nfc)
334 writel(0, nfc->regs + NFC_REG_ECC_CTL);
335 writel(NFC_RESET, nfc->regs + NFC_REG_CTL);
337 ret = readl_poll_timeout(nfc->regs + NFC_REG_CTL, ctl,
341 dev_err(nfc->dev, "wait for NAND controller reset timedout\n");
346 static int sunxi_nfc_dma_op_prepare(struct sunxi_nfc *nfc, const void *buf,
362 ret = dma_map_sg(nfc->dev, sg, 1, ddir);
366 dmad = dmaengine_prep_slave_sg(nfc->dmac, sg, 1, tdir, DMA_CTRL_ACK);
372 writel(readl(nfc->regs + NFC_REG_CTL) | NFC_RAM_METHOD,
373 nfc->regs + NFC_REG_CTL);
374 writel(nchunks, nfc->regs + NFC_REG_SECTOR_NUM);
375 writel(chunksize, nfc->regs + NFC_REG_CNT);
376 if (nfc->caps->extra_mbus_conf)
377 writel(chunksize * nchunks, nfc->regs + NFC_REG_MDMA_CNT);
388 writel(readl(nfc->regs + NFC_REG_CTL) & ~NFC_RAM_METHOD,
389 nfc->regs + NFC_REG_CTL);
392 dma_unmap_sg(nfc->dev, sg, 1, ddir);
396 static void sunxi_nfc_dma_op_cleanup(struct sunxi_nfc *nfc,
400 dma_unmap_sg(nfc->dev, sg, 1, ddir);
401 writel(readl(nfc->regs + NFC_REG_CTL) & ~NFC_RAM_METHOD,
402 nfc->regs + NFC_REG_CTL);
409 struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
416 ctl = readl(nfc->regs + NFC_REG_CTL) &
424 writel(mtd->writesize, nfc->regs + NFC_REG_SPARE_AREA);
426 if (nfc->clk_rate != sunxi_nand->clk_rate) {
427 clk_set_rate(nfc->mod_clk, sunxi_nand->clk_rate);
428 nfc->clk_rate = sunxi_nand->clk_rate;
431 writel(sunxi_nand->timing_ctl, nfc->regs + NFC_REG_TIMING_CTL);
432 writel(sunxi_nand->timing_cfg, nfc->regs + NFC_REG_TIMING_CFG);
433 writel(ctl, nfc->regs + NFC_REG_CTL);
439 struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
450 ret = sunxi_nfc_wait_cmd_fifo_empty(nfc);
454 writel(cnt, nfc->regs + NFC_REG_CNT);
456 writel(tmp, nfc->regs + NFC_REG_CMD);
462 ret = sunxi_nfc_wait_events(nfc, NFC_CMD_INT_FLAG, poll, 0);
467 memcpy_fromio(buf + offs, nfc->regs + NFC_RAM0_BASE,
477 struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
488 ret = sunxi_nfc_wait_cmd_fifo_empty(nfc);
492 writel(cnt, nfc->regs + NFC_REG_CNT);
493 memcpy_toio(nfc->regs + NFC_RAM0_BASE, buf + offs, cnt);
496 writel(tmp, nfc->regs + NFC_REG_CMD);
502 ret = sunxi_nfc_wait_events(nfc, NFC_CMD_INT_FLAG, poll, 0);
615 struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
616 u32 ecc_ctl = readl(nfc->regs + NFC_REG_ECC_CTL);
622 ecc_ctl = readl(nfc->regs + NFC_REG_ECC_CTL);
624 ecc_ctl = readl(nfc->regs + NFC_REG_ECC_CTL) & ~NFC_RANDOM_SEED_MSK;
625 writel(ecc_ctl | NFC_RANDOM_SEED(state), nfc->regs + NFC_REG_ECC_CTL);
630 struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
635 writel(readl(nfc->regs + NFC_REG_ECC_CTL) | NFC_RANDOM_EN,
636 nfc->regs + NFC_REG_ECC_CTL);
641 struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
646 writel(readl(nfc->regs + NFC_REG_ECC_CTL) & ~NFC_RANDOM_EN,
647 nfc->regs + NFC_REG_ECC_CTL);
679 struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
683 ecc_ctl = readl(nfc->regs + NFC_REG_ECC_CTL);
692 writel(ecc_ctl, nfc->regs + NFC_REG_ECC_CTL);
697 struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
699 writel(readl(nfc->regs + NFC_REG_ECC_CTL) & ~NFC_ECC_EN,
700 nfc->regs + NFC_REG_ECC_CTL);
719 struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
721 sunxi_nfc_user_data_to_buf(readl(nfc->regs + NFC_REG_USER_DATA(step)),
733 struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
744 nfc->regs + NFC_REG_USER_DATA(step));
763 struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
775 if (unlikely(!(readl(nfc->regs + NFC_REG_PAT_ID) & 0x1))) {
791 tmp = readl(nfc->regs + NFC_REG_ECC_ERR_CNT(step));
803 struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
817 ret = sunxi_nfc_wait_cmd_fifo_empty(nfc);
823 nfc->regs + NFC_REG_CMD);
825 ret = sunxi_nfc_wait_events(nfc, NFC_CMD_INT_FLAG, false, 0);
833 readl(nfc->regs + NFC_REG_ECC_ST),
847 memcpy_fromio(data, nfc->regs + NFC_RAM0_BASE,
859 memcpy_fromio(data, nfc->regs + NFC_RAM0_BASE, ecc->size);
908 struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
916 ret = sunxi_nfc_wait_cmd_fifo_empty(nfc);
920 ret = sunxi_nfc_dma_op_prepare(nfc, buf, ecc->size, nchunks,
930 NAND_CMD_READSTART, nfc->regs + NFC_REG_RCMD_SET);
932 dma_async_issue_pending(nfc->dmac);
935 nfc->regs + NFC_REG_CMD);
937 ret = sunxi_nfc_wait_events(nfc, NFC_CMD_INT_FLAG, false, 0);
939 dmaengine_terminate_all(nfc->dmac);
944 sunxi_nfc_dma_op_cleanup(nfc, DMA_FROM_DEVICE, &sg);
949 status = readl(nfc->regs + NFC_REG_ECC_ST);
1032 struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
1044 ret = sunxi_nfc_wait_cmd_fifo_empty(nfc);
1053 nfc->regs + NFC_REG_CMD);
1055 ret = sunxi_nfc_wait_events(nfc, NFC_CMD_INT_FLAG, false, 0);
1276 struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
1283 ret = sunxi_nfc_wait_cmd_fifo_empty(nfc);
1287 ret = sunxi_nfc_dma_op_prepare(nfc, buf, ecc->size, ecc->steps,
1305 nfc->regs + NFC_REG_WCMD_SET);
1307 dma_async_issue_pending(nfc->dmac);
1311 nfc->regs + NFC_REG_CMD);
1313 ret = sunxi_nfc_wait_events(nfc, NFC_CMD_INT_FLAG, false, 0);
1315 dmaengine_terminate_all(nfc->dmac);
1320 sunxi_nfc_dma_op_cleanup(nfc, DMA_TO_DEVICE, &sg);
1383 struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
1483 dev_err(nfc->dev, "unsupported tWB\n");
1489 dev_err(nfc->dev, "unsupported tADL\n");
1495 dev_err(nfc->dev, "unsupported tWHR\n");
1502 dev_err(nfc->dev, "unsupported tRHW\n");
1528 real_clk_rate = clk_round_rate(nfc->mod_clk, sunxi_nand->clk_rate);
1530 dev_err(nfc->dev, "Unable to round clk %lu\n",
1610 struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
1673 dev_err(nfc->dev, "unsupported strength\n");
1698 if (nfc->dmac) {
1777 struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
1823 memcpy_toio(nfc->regs + NFC_RAM0_BASE,
1838 ret = sunxi_nfc_wait_cmd_fifo_empty(nfc);
1843 writel(addrs[0], nfc->regs + NFC_REG_ADDR_LOW);
1844 writel(addrs[1], nfc->regs + NFC_REG_ADDR_HIGH);
1849 nfc->regs +
1854 writel(cnt, nfc->regs + NFC_REG_CNT);
1856 writel(cmd, nfc->regs + NFC_REG_CMD);
1858 ret = sunxi_nfc_wait_events(nfc, NFC_CMD_INT_FLAG,
1865 memcpy_fromio(inbuf, nfc->regs + NFC_RAM0_BASE, cnt);
1930 static int sunxi_nand_chip_init(struct device *dev, struct sunxi_nfc *nfc,
1974 if (test_and_set_bit(tmp, &nfc->assigned_cs)) {
1990 nand->controller = &nfc->controller;
2014 list_add_tail(&sunxi_nand->node, &nfc->chips);
2019 static int sunxi_nand_chips_init(struct device *dev, struct sunxi_nfc *nfc)
2032 ret = sunxi_nand_chip_init(dev, nfc, nand_np);
2042 static void sunxi_nand_chips_cleanup(struct sunxi_nfc *nfc)
2048 while (!list_empty(&nfc->chips)) {
2049 sunxi_nand = list_first_entry(&nfc->chips,
2065 struct sunxi_nfc *nfc;
2069 nfc = devm_kzalloc(dev, sizeof(*nfc), GFP_KERNEL);
2070 if (!nfc)
2073 nfc->dev = dev;
2074 nand_controller_init(&nfc->controller);
2075 INIT_LIST_HEAD(&nfc->chips);
2078 nfc->regs = devm_ioremap_resource(dev, r);
2079 if (IS_ERR(nfc->regs))
2080 return PTR_ERR(nfc->regs);
2086 nfc->ahb_clk = devm_clk_get(dev, "ahb");
2087 if (IS_ERR(nfc->ahb_clk)) {
2089 return PTR_ERR(nfc->ahb_clk);
2092 ret = clk_prepare_enable(nfc->ahb_clk);
2096 nfc->mod_clk = devm_clk_get(dev, "mod");
2097 if (IS_ERR(nfc->mod_clk)) {
2099 ret = PTR_ERR(nfc->mod_clk);
2103 ret = clk_prepare_enable(nfc->mod_clk);
2107 nfc->reset = devm_reset_control_get_optional_exclusive(dev, "ahb");
2108 if (IS_ERR(nfc->reset)) {
2109 ret = PTR_ERR(nfc->reset);
2113 ret = reset_control_deassert(nfc->reset);
2119 nfc->caps = of_device_get_match_data(&pdev->dev);
2120 if (!nfc->caps) {
2125 ret = sunxi_nfc_rst(nfc);
2129 writel(0, nfc->regs + NFC_REG_INT);
2131 0, "sunxi-nand", nfc);
2135 nfc->dmac = dma_request_chan(dev, "rxtx");
2136 if (IS_ERR(nfc->dmac)) {
2137 ret = PTR_ERR(nfc->dmac);
2143 nfc->dmac = NULL;
2147 dmac_cfg.src_addr = r->start + nfc->caps->reg_io_data;
2151 dmac_cfg.src_maxburst = nfc->caps->dma_maxburst;
2152 dmac_cfg.dst_maxburst = nfc->caps->dma_maxburst;
2153 dmaengine_slave_config(nfc->dmac, &dmac_cfg);
2155 if (nfc->caps->extra_mbus_conf)
2156 writel(readl(nfc->regs + NFC_REG_CTL) |
2157 NFC_DMA_TYPE_NORMAL, nfc->regs + NFC_REG_CTL);
2160 platform_set_drvdata(pdev, nfc);
2162 ret = sunxi_nand_chips_init(dev, nfc);
2171 if (nfc->dmac)
2172 dma_release_channel(nfc->dmac);
2174 reset_control_assert(nfc->reset);
2176 clk_disable_unprepare(nfc->mod_clk);
2178 clk_disable_unprepare(nfc->ahb_clk);
2185 struct sunxi_nfc *nfc = platform_get_drvdata(pdev);
2187 sunxi_nand_chips_cleanup(nfc);
2189 reset_control_assert(nfc->reset);
2191 if (nfc->dmac)
2192 dma_release_channel(nfc->dmac);
2193 clk_disable_unprepare(nfc->mod_clk);
2194 clk_disable_unprepare(nfc->ahb_clk);