Lines Matching defs:timings
1384 const struct nand_sdr_timings *timings;
1389 timings = nand_get_sdr_timings(conf);
1390 if (IS_ERR(timings))
1394 if (timings->tCLS_min > min_clk_period)
1395 min_clk_period = timings->tCLS_min;
1398 if (timings->tCLH_min > min_clk_period)
1399 min_clk_period = timings->tCLH_min;
1402 if (timings->tCS_min > min_clk_period)
1403 min_clk_period = timings->tCS_min;
1406 if (timings->tCH_min > min_clk_period)
1407 min_clk_period = timings->tCH_min;
1410 if (timings->tWP_min > min_clk_period)
1411 min_clk_period = timings->tWP_min;
1414 if (timings->tWH_min > min_clk_period)
1415 min_clk_period = timings->tWH_min;
1418 if (timings->tALS_min > min_clk_period)
1419 min_clk_period = timings->tALS_min;
1422 if (timings->tDS_min > min_clk_period)
1423 min_clk_period = timings->tDS_min;
1426 if (timings->tDH_min > min_clk_period)
1427 min_clk_period = timings->tDH_min;
1430 if (timings->tRR_min > (min_clk_period * 3))
1431 min_clk_period = DIV_ROUND_UP(timings->tRR_min, 3);
1434 if (timings->tALH_min > min_clk_period)
1435 min_clk_period = timings->tALH_min;
1438 if (timings->tRP_min > min_clk_period)
1439 min_clk_period = timings->tRP_min;
1442 if (timings->tREH_min > min_clk_period)
1443 min_clk_period = timings->tREH_min;
1446 if (timings->tRC_min > (min_clk_period * 2))
1447 min_clk_period = DIV_ROUND_UP(timings->tRC_min, 2);
1450 if (timings->tWC_min > (min_clk_period * 2))
1451 min_clk_period = DIV_ROUND_UP(timings->tWC_min, 2);
1454 if (timings->tWB_max > (min_clk_period * 20))
1455 min_clk_period = DIV_ROUND_UP(timings->tWB_max, 20);
1457 if (timings->tADL_min > (min_clk_period * 32))
1458 min_clk_period = DIV_ROUND_UP(timings->tADL_min, 32);
1460 if (timings->tWHR_min > (min_clk_period * 32))
1461 min_clk_period = DIV_ROUND_UP(timings->tWHR_min, 32);
1463 if (timings->tRHW_min > (min_clk_period * 20))
1464 min_clk_period = DIV_ROUND_UP(timings->tRHW_min, 20);
1475 * 2/ Use EDO mode (only works if timings->tRLOH > 0)
1477 if (timings->tREA_max > min_clk_period && !timings->tRLOH_min)
1478 min_clk_period = timings->tREA_max;
1480 tWB = sunxi_nand_lookup_timing(tWB_lut, timings->tWB_max,
1487 tADL = DIV_ROUND_UP(timings->tADL_min, min_clk_period) >> 3;
1493 tWHR = DIV_ROUND_UP(timings->tWHR_min, min_clk_period) >> 3;
1499 tRHW = sunxi_nand_lookup_timing(tRHW_lut, timings->tRHW_min,
1539 * output cycle timings shall be used if the host drives tRC less than
1543 if (min_clk_period * 2 < 30 || min_clk_period * 1000 < timings->tREA_max)