Lines Matching refs:info
113 * @info: Link back to the hardware information.
118 struct s3c2410_nand_info *info;
151 /* mtd info */
156 /* device info */
200 return s3c2410_nand_mtd_toours(mtd)->info;
213 static inline int allow_clk_suspend(struct s3c2410_nand_info *info)
224 * @info: The controller instance.
227 static void s3c2410_nand_clk_set_state(struct s3c2410_nand_info *info,
230 if (!allow_clk_suspend(info) && new_state == CLOCK_SUSPEND)
233 if (info->clk_state == CLOCK_ENABLE) {
235 clk_disable_unprepare(info->clk);
238 clk_prepare_enable(info->clk);
241 info->clk_state = new_state;
282 * @info: The controller instance.
288 static int s3c2410_nand_setrate(struct s3c2410_nand_info *info)
290 struct s3c2410_platform_nand *plat = info->platform;
291 int tacls_max = (info->cpu_type == TYPE_S3C2412) ? 8 : 4;
293 unsigned long clkrate = clk_get_rate(info->clk);
299 info->clk_rate = clkrate;
314 dev_err(info->device, "cannot get suitable timings\n");
318 dev_info(info->device, "Tacls=%d, %dns Twrph0=%d %dns, Twrph1=%d %dns\n",
322 switch (info->cpu_type) {
350 cfg = readl(info->regs + S3C2410_NFCONF);
353 writel(cfg, info->regs + S3C2410_NFCONF);
357 dev_dbg(info->device, "NF_CONF is 0x%lx\n", cfg);
364 * @info: The hardware state.
369 static int s3c2410_nand_inithw(struct s3c2410_nand_info *info)
373 ret = s3c2410_nand_setrate(info);
377 switch (info->cpu_type) {
386 writel(S3C2440_NFCONT_ENABLE, info->regs + S3C2440_NFCONT);
407 struct s3c2410_nand_info *info;
412 info = nmtd->info;
415 s3c2410_nand_clk_set_state(info, CLOCK_ENABLE);
417 cur = readl(info->sel_reg);
420 cur |= info->sel_bit;
423 dev_err(info->device, "invalid chip %d\n", chip);
427 if (info->platform != NULL) {
428 if (info->platform->select_chip != NULL)
429 (info->platform->select_chip) (nmtd->set, chip);
432 cur &= ~info->sel_bit;
435 writel(cur, info->sel_reg);
438 s3c2410_nand_clk_set_state(info, CLOCK_SUSPEND);
450 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
456 writeb(cmd, info->regs + S3C2410_NFCMD);
458 writeb(cmd, info->regs + S3C2410_NFADDR);
467 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
473 writeb(cmd, info->regs + S3C2440_NFCMD);
475 writeb(cmd, info->regs + S3C2440_NFADDR);
486 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
487 return readb(info->regs + S3C2410_NFSTAT) & S3C2410_NFSTAT_BUSY;
493 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
494 return readb(info->regs + S3C2440_NFSTAT) & S3C2440_NFSTAT_READY;
500 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
501 return readb(info->regs + S3C2412_NFSTAT) & S3C2412_NFSTAT_READY;
510 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
532 && info->platform->ignore_unset_ecc)
559 dev_dbg(info->device, "correcting error bit %d, byte %d\n",
588 struct s3c2410_nand_info *info;
591 info = s3c2410_nand_mtd_toinfo(nand_to_mtd(chip));
592 ctrl = readl(info->regs + S3C2410_NFCONF);
594 writel(ctrl, info->regs + S3C2410_NFCONF);
599 struct s3c2410_nand_info *info;
602 info = s3c2410_nand_mtd_toinfo(nand_to_mtd(chip));
603 ctrl = readl(info->regs + S3C2440_NFCONT);
605 info->regs + S3C2440_NFCONT);
610 struct s3c2410_nand_info *info;
613 info = s3c2410_nand_mtd_toinfo(nand_to_mtd(chip));
614 ctrl = readl(info->regs + S3C2440_NFCONT);
615 writel(ctrl | S3C2440_NFCONT_INITECC, info->regs + S3C2440_NFCONT);
622 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
624 ecc_code[0] = readb(info->regs + S3C2410_NFECC + 0);
625 ecc_code[1] = readb(info->regs + S3C2410_NFECC + 1);
626 ecc_code[2] = readb(info->regs + S3C2410_NFECC + 2);
637 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
638 unsigned long ecc = readl(info->regs + S3C2412_NFMECC0);
653 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
654 unsigned long ecc = readl(info->regs + S3C2440_NFMECC0);
677 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
679 readsl(info->regs + S3C2440_NFDATA, buf, len >> 2);
686 *buf++ = readb(info->regs + S3C2440_NFDATA);
700 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
702 writesl(info->regs + S3C2440_NFDATA, buf, len >> 2);
709 writeb(*buf, info->regs + S3C2440_NFDATA);
720 struct s3c2410_nand_info *info;
723 info = container_of(nb, struct s3c2410_nand_info, freq_transition);
724 newclk = clk_get_rate(info->clk);
726 if ((val == CPUFREQ_POSTCHANGE && newclk < info->clk_rate) ||
727 (val == CPUFREQ_PRECHANGE && newclk > info->clk_rate)) {
728 s3c2410_nand_setrate(info);
734 static inline int s3c2410_nand_cpufreq_register(struct s3c2410_nand_info *info)
736 info->freq_transition.notifier_call = s3c2410_nand_cpufreq_transition;
738 return cpufreq_register_notifier(&info->freq_transition,
743 s3c2410_nand_cpufreq_deregister(struct s3c2410_nand_info *info)
745 cpufreq_unregister_notifier(&info->freq_transition,
750 static inline int s3c2410_nand_cpufreq_register(struct s3c2410_nand_info *info)
756 s3c2410_nand_cpufreq_deregister(struct s3c2410_nand_info *info)
765 struct s3c2410_nand_info *info = to_nand_info(pdev);
767 if (info == NULL)
770 s3c2410_nand_cpufreq_deregister(info);
776 if (info->mtds != NULL) {
777 struct s3c2410_nand_mtd *ptr = info->mtds;
780 for (mtdno = 0; mtdno < info->mtd_count; mtdno++, ptr++) {
789 if (!IS_ERR(info->clk))
790 s3c2410_nand_clk_set_state(info, CLOCK_DISABLE);
795 static int s3c2410_nand_add_partition(struct s3c2410_nand_info *info,
815 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
816 struct s3c2410_platform_nand *pdata = info->platform;
832 return s3c2410_nand_setrate(info);
837 * @info: The base NAND controller the chip is on.
841 * Initialise the given @nmtd from the information in @info and @set. This
845 static void s3c2410_nand_init_chip(struct s3c2410_nand_info *info,
849 struct device_node *np = info->device->of_node;
851 void __iomem *regs = info->regs;
861 chip->controller = &info->controller;
870 switch (info->cpu_type) {
873 info->sel_reg = regs + S3C2410_NFCONF;
874 info->sel_bit = S3C2410_NFCONF_nFCE;
881 info->sel_reg = regs + S3C2440_NFCONT;
882 info->sel_bit = S3C2440_NFCONT_nFCE;
891 info->sel_reg = regs + S3C2440_NFCONT;
892 info->sel_bit = S3C2412_NFCONT_nFCE0;
897 dev_info(info->device, "System booted from NAND\n");
904 nmtd->info = info;
907 chip->ecc.engine_type = info->platform->engine_type;
930 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
935 dev_info(info->device, "ECC disabled\n");
946 dev_info(info->device, "soft ECC\n");
954 switch (info->cpu_type) {
971 dev_dbg(info->device, "chip %p => page shift %d\n",
986 dev_info(info->device, "hardware ECC\n");
990 dev_err(info->device, "invalid ECC mode!\n");
1025 struct s3c2410_nand_info *info = platform_get_drvdata(pdev);
1033 info->cpu_type = devtype_data->type;
1067 struct s3c2410_nand_info *info = platform_get_drvdata(pdev);
1069 info->cpu_type = platform_get_device_id(pdev)->driver_data;
1084 struct s3c2410_nand_info *info;
1093 info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
1094 if (info == NULL) {
1099 platform_set_drvdata(pdev, info);
1101 nand_controller_init(&info->controller);
1102 info->controller.ops = &s3c24xx_nand_controller_ops;
1106 info->clk = devm_clk_get(&pdev->dev, "nand");
1107 if (IS_ERR(info->clk)) {
1113 s3c2410_nand_clk_set_state(info, CLOCK_ENABLE);
1131 info->device = &pdev->dev;
1132 info->platform = plat;
1134 info->regs = devm_ioremap_resource(&pdev->dev, res);
1135 if (IS_ERR(info->regs)) {
1136 err = PTR_ERR(info->regs);
1140 dev_dbg(&pdev->dev, "mapped registers at %p\n", info->regs);
1150 info->mtd_count = nr_sets;
1154 size = nr_sets * sizeof(*info->mtds);
1155 info->mtds = devm_kzalloc(&pdev->dev, size, GFP_KERNEL);
1156 if (info->mtds == NULL) {
1163 nmtd = info->mtds;
1168 pr_debug("initialising set %d (%p, info %p)\n",
1169 setno, nmtd, info);
1172 s3c2410_nand_init_chip(info, nmtd, sets);
1178 s3c2410_nand_add_partition(info, nmtd, sets);
1182 err = s3c2410_nand_inithw(info);
1186 err = s3c2410_nand_cpufreq_register(info);
1192 if (allow_clk_suspend(info)) {
1194 s3c2410_nand_clk_set_state(info, CLOCK_SUSPEND);
1212 struct s3c2410_nand_info *info = platform_get_drvdata(dev);
1214 if (info) {
1215 info->save_sel = readl(info->sel_reg);
1222 writel(info->save_sel | info->sel_bit, info->sel_reg);
1224 s3c2410_nand_clk_set_state(info, CLOCK_DISABLE);
1232 struct s3c2410_nand_info *info = platform_get_drvdata(dev);
1235 if (info) {
1236 s3c2410_nand_clk_set_state(info, CLOCK_ENABLE);
1237 s3c2410_nand_inithw(info);
1241 sel = readl(info->sel_reg);
1242 sel &= ~info->sel_bit;
1243 sel |= info->save_sel & info->sel_bit;
1244 writel(sel, info->sel_reg);
1246 s3c2410_nand_clk_set_state(info, CLOCK_SUSPEND);