Lines Matching defs:set
112 * @set: The platform information supplied for this set of NAND chips.
117 struct s3c2410_nand_set *set;
225 * @new_state: State to which clock should be set.
284 * Given the information supplied by the platform, calculate and set
294 unsigned long set, cfg, mask;
327 set = S3C2410_NFCONF_EN;
328 set |= S3C2410_NFCONF_TACLS(tacls - 1);
329 set |= S3C2410_NFCONF_TWRPH0(twrph0 - 1);
330 set |= S3C2410_NFCONF_TWRPH1(twrph1 - 1);
339 set = S3C2440_NFCONF_TACLS(tacls - 1);
340 set |= S3C2440_NFCONF_TWRPH0(twrph0 - 1);
341 set |= S3C2440_NFCONF_TWRPH1(twrph1 - 1);
352 cfg |= set;
367 * to setup the hardware access speeds and set the controller to be enabled.
422 if (nmtd->set != NULL && chip > nmtd->set->nr_chips) {
429 (info->platform->select_chip) (nmtd->set, chip);
797 struct s3c2410_nand_set *set)
799 if (set) {
802 mtdinfo->name = set->name;
804 return mtd_device_register(mtdinfo, set->partitions,
805 set->nr_partitions);
839 * @set: The information passed from the board specific platform data.
841 * Initialise the given @nmtd from the information in @info and @set. This
847 struct s3c2410_nand_set *set)
853 nand_set_flash_node(chip, set->of_node);
860 chip->options = set->options;
905 nmtd->set = set;
913 if (set->flash_bbt)
940 * This driver expects Hamming based ECC when engine_type is set
1168 pr_debug("initialising set %d (%p, info %p)\n",