Lines Matching defs:ret
735 int ret;
765 ret = dma_map_sg(nandc->dev, sgl, sgl_cnt, desc->dir);
766 if (ret == 0) {
812 int i, ret;
847 ret = prepare_bam_async_desc(nandc, nandc->cmd_chan,
850 if (ret)
851 return ret;
866 int ret;
883 ret = prepare_bam_async_desc(nandc, nandc->tx_chan,
885 if (ret)
886 return ret;
902 int ret;
920 ret = dma_map_sg(nandc->dev, sgl, 1, desc->dir);
921 if (ret == 0) {
922 ret = -ENOMEM;
939 ret = dmaengine_slave_config(nandc->chan, &slave_conf);
940 if (ret) {
948 ret = -EINVAL;
960 return ret;
1444 int ret = 0;
1450 ret = reset(host);
1456 ret = read_id(host, column);
1461 ret = nandc_param(host);
1466 ret = erase_block(host, page_addr);
1491 if (ret) {
1499 ret = submit_descs(nandc);
1500 if (ret)
1593 int ret, reg_off = FLASH_BUF_ACC, read_loc = 0;
1642 ret = submit_descs(nandc);
1644 if (ret) {
1646 return ret;
1676 int cw, data_size, oob_size, ret = 0;
1699 ret = qcom_nandc_read_cw_raw(mtd, chip, cw_data_buf,
1701 if (ret)
1702 return ret;
1708 ret = nand_check_erased_ecc_chunk(cw_data_buf, data_size,
1712 if (ret < 0) {
1715 mtd->ecc_stats.corrected += ret;
1716 max_bitflips = max_t(unsigned int, max_bitflips, ret);
1838 int i, ret;
1897 ret = submit_descs(nandc);
1900 if (ret) {
1902 return ret;
1918 int ret;
1934 ret = submit_descs(nandc);
1935 if (ret)
1940 return ret;
1967 int cw, ret;
1971 ret = qcom_nandc_read_cw_raw(mtd, chip, data_buf, oob_buf,
1973 if (ret)
1974 return ret;
2008 int i, ret;
2058 ret = submit_descs(nandc);
2059 if (ret)
2064 if (!ret)
2065 ret = nand_prog_page_end_op(chip);
2067 return ret;
2080 int i, ret;
2131 ret = submit_descs(nandc);
2132 if (ret)
2137 if (!ret)
2138 ret = nand_prog_page_end_op(chip);
2140 return ret;
2158 int ret;
2180 ret = submit_descs(nandc);
2184 if (ret) {
2198 int page, ret, bbpos, bad = 0;
2211 ret = copy_last_cw(host, page);
2212 if (ret)
2235 int page, ret;
2259 ret = submit_descs(nandc);
2263 if (ret) {
2282 u8 ret = 0x0;
2285 ret = host->status;
2289 return ret;
2293 ret = buf[nandc->buf_start++];
2295 return ret;
2471 int cwperpage, bad_block_byte, ret;
2484 ret = nand_ecc_choose_conf(chip, &qcom_nandc_ecc_caps,
2486 if (ret) {
2488 return ret;
2659 int ret;
2661 ret = dma_set_coherent_mask(nandc->dev, DMA_BIT_MASK(32));
2662 if (ret) {
2664 return ret;
2704 ret = PTR_ERR(nandc->tx_chan);
2706 dev_err_probe(nandc->dev, ret,
2713 ret = PTR_ERR(nandc->rx_chan);
2715 dev_err_probe(nandc->dev, ret,
2722 ret = PTR_ERR(nandc->cmd_chan);
2724 dev_err_probe(nandc->dev, ret,
2740 ret = -ENOMEM;
2746 ret = PTR_ERR(nandc->chan);
2748 dev_err_probe(nandc->dev, ret,
2750 return ret;
2763 return ret;
2808 int ret;
2810 ret = of_property_read_u32(dn, "reg", &host->cs);
2811 if (ret) {
2850 ret = nand_scan(chip, 1);
2851 if (ret)
2852 return ret;
2864 ret = mtd_device_register(mtd, NULL, 0);
2865 if (ret)
2868 return ret;
2876 int ret = -ENODEV;
2885 ret = qcom_nand_host_init_and_register(nandc, host, child);
2886 if (ret) {
2894 return ret;
2902 int ret;
2905 ret = of_property_read_u32(np, "qcom,cmd-crci",
2907 if (ret) {
2909 return ret;
2912 ret = of_property_read_u32(np, "qcom,data-crci",
2914 if (ret) {
2916 return ret;
2929 int ret;
2954 ret = qcom_nandc_parse_dt(pdev);
2955 if (ret)
2956 return ret;
2970 ret = clk_prepare_enable(nandc->core_clk);
2971 if (ret)
2974 ret = clk_prepare_enable(nandc->aon_clk);
2975 if (ret)
2978 ret = qcom_nandc_alloc(nandc);
2979 if (ret)
2982 ret = qcom_nandc_setup(nandc);
2983 if (ret)
2986 ret = qcom_probe_nand_devices(nandc);
2987 if (ret)
3001 return ret;
3010 int ret;
3014 ret = mtd_device_unregister(nand_to_mtd(chip));
3015 WARN_ON(ret);