Lines Matching defs:nandc
182 #define nandc_set_read_loc(nandc, reg, offset, size, is_last) \
183 nandc_set_reg(nandc, NAND_READ_LOCATION_##reg, \
192 #define dev_cmd_reg_addr(nandc, reg) ((nandc)->props->dev_cmd_reg_start + (reg))
472 static void free_bam_transaction(struct qcom_nand_controller *nandc)
474 struct bam_transaction *bam_txn = nandc->bam_txn;
476 devm_kfree(nandc->dev, bam_txn);
481 alloc_bam_transaction(struct qcom_nand_controller *nandc)
485 unsigned int num_cw = nandc->max_cwperpage;
494 bam_txn_buf = devm_kzalloc(nandc->dev, bam_txn_size, GFP_KERNEL);
517 static void clear_bam_transaction(struct qcom_nand_controller *nandc)
519 struct bam_transaction *bam_txn = nandc->bam_txn;
521 if (!nandc->props->is_bam)
535 sg_init_table(bam_txn->cmd_sgl, nandc->max_cwperpage *
537 sg_init_table(bam_txn->data_sgl, nandc->max_cwperpage *
573 static inline u32 nandc_read(struct qcom_nand_controller *nandc, int offset)
575 return ioread32(nandc->base + offset);
578 static inline void nandc_write(struct qcom_nand_controller *nandc, int offset,
581 iowrite32(val, nandc->base + offset);
584 static inline void nandc_read_buffer_sync(struct qcom_nand_controller *nandc,
587 if (!nandc->props->is_bam)
591 dma_sync_single_for_cpu(nandc->dev, nandc->reg_read_dma,
593 sizeof(*nandc->reg_read_buf),
596 dma_sync_single_for_device(nandc->dev, nandc->reg_read_dma,
598 sizeof(*nandc->reg_read_buf),
648 static void nandc_set_reg(struct qcom_nand_controller *nandc, int offset,
651 struct nandc_regs *regs = nandc->regs;
664 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
669 nandc_set_reg(nandc, NAND_ADDR0, page << 16 | column);
670 nandc_set_reg(nandc, NAND_ADDR1, page >> 16 & 0xff);
683 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
709 nandc_set_reg(nandc, NAND_FLASH_CMD, cmd);
710 nandc_set_reg(nandc, NAND_DEV0_CFG0, cfg0);
711 nandc_set_reg(nandc, NAND_DEV0_CFG1, cfg1);
712 nandc_set_reg(nandc, NAND_DEV0_ECC_CFG, ecc_bch_cfg);
713 nandc_set_reg(nandc, NAND_EBI2_ECC_BUF_CFG, host->ecc_buf_cfg);
714 nandc_set_reg(nandc, NAND_FLASH_STATUS, host->clrflashstatus);
715 nandc_set_reg(nandc, NAND_READ_STATUS, host->clrreadstatus);
716 nandc_set_reg(nandc, NAND_EXEC_CMD, 1);
719 nandc_set_read_loc(nandc, 0, 0, host->use_ecc ?
728 static int prepare_bam_async_desc(struct qcom_nand_controller *nandc,
736 struct bam_transaction *bam_txn = nandc->bam_txn;
744 if (chan == nandc->cmd_chan) {
750 } else if (chan == nandc->tx_chan) {
765 ret = dma_map_sg(nandc->dev, sgl, sgl_cnt, desc->dir);
767 dev_err(nandc->dev, "failure in mapping desc\n");
779 dev_err(nandc->dev, "failure in prep desc\n");
780 dma_unmap_sg(nandc->dev, sgl, sgl_cnt, desc->dir);
788 if (chan == nandc->cmd_chan)
793 list_add_tail(&desc->node, &nandc->desc_list);
807 static int prep_bam_dma_desc_cmd(struct qcom_nand_controller *nandc, bool read,
814 struct bam_transaction *bam_txn = nandc->bam_txn;
822 nandc_reg_phys(nandc, reg_off + 4 * i),
824 reg_buf_dma_addr(nandc,
828 nandc_reg_phys(nandc, reg_off + 4 * i),
847 ret = prepare_bam_async_desc(nandc, nandc->cmd_chan,
862 static int prep_bam_dma_desc_data(struct qcom_nand_controller *nandc, bool read,
867 struct bam_transaction *bam_txn = nandc->bam_txn;
883 ret = prepare_bam_async_desc(nandc, nandc->tx_chan,
893 static int prep_adm_dma_desc(struct qcom_nand_controller *nandc, bool read,
920 ret = dma_map_sg(nandc->dev, sgl, 1, desc->dir);
931 slave_conf.src_addr = nandc->base_dma + reg_off;
932 slave_conf.slave_id = nandc->data_crci;
935 slave_conf.dst_addr = nandc->base_dma + reg_off;
936 slave_conf.slave_id = nandc->cmd_crci;
939 ret = dmaengine_slave_config(nandc->chan, &slave_conf);
941 dev_err(nandc->dev, "failed to configure dma channel\n");
945 dma_desc = dmaengine_prep_slave_sg(nandc->chan, sgl, 1, dir_eng, 0);
947 dev_err(nandc->dev, "failed to prepare desc\n");
954 list_add_tail(&desc->node, &nandc->desc_list);
971 static int read_reg_dma(struct qcom_nand_controller *nandc, int first,
977 vaddr = nandc->reg_read_buf + nandc->reg_read_pos;
978 nandc->reg_read_pos += num_regs;
981 first = dev_cmd_reg_addr(nandc, first);
983 if (nandc->props->is_bam)
984 return prep_bam_dma_desc_cmd(nandc, true, first, vaddr,
990 return prep_adm_dma_desc(nandc, true, first, vaddr,
1002 static int write_reg_dma(struct qcom_nand_controller *nandc, int first,
1006 struct nandc_regs *regs = nandc->regs;
1022 first = dev_cmd_reg_addr(nandc, NAND_DEV_CMD1);
1025 first = dev_cmd_reg_addr(nandc, NAND_DEV_CMD_VLD);
1027 if (nandc->props->is_bam)
1028 return prep_bam_dma_desc_cmd(nandc, false, first, vaddr,
1034 return prep_adm_dma_desc(nandc, false, first, vaddr,
1047 static int read_data_dma(struct qcom_nand_controller *nandc, int reg_off,
1050 if (nandc->props->is_bam)
1051 return prep_bam_dma_desc_data(nandc, true, vaddr, size, flags);
1053 return prep_adm_dma_desc(nandc, true, reg_off, vaddr, size, false);
1065 static int write_data_dma(struct qcom_nand_controller *nandc, int reg_off,
1068 if (nandc->props->is_bam)
1069 return prep_bam_dma_desc_data(nandc, false, vaddr, size, flags);
1071 return prep_adm_dma_desc(nandc, false, reg_off, vaddr, size, false);
1078 static void config_nand_page_read(struct qcom_nand_controller *nandc)
1080 write_reg_dma(nandc, NAND_ADDR0, 2, 0);
1081 write_reg_dma(nandc, NAND_DEV0_CFG0, 3, 0);
1082 write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1, 0);
1083 write_reg_dma(nandc, NAND_ERASED_CW_DETECT_CFG, 1, 0);
1084 write_reg_dma(nandc, NAND_ERASED_CW_DETECT_CFG, 1,
1093 config_nand_cw_read(struct qcom_nand_controller *nandc, bool use_ecc)
1095 if (nandc->props->is_bam)
1096 write_reg_dma(nandc, NAND_READ_LOCATION_0, 4,
1099 write_reg_dma(nandc, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL);
1100 write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
1103 read_reg_dma(nandc, NAND_FLASH_STATUS, 2, 0);
1104 read_reg_dma(nandc, NAND_ERASED_CW_DETECT_STATUS, 1,
1107 read_reg_dma(nandc, NAND_FLASH_STATUS, 1, NAND_BAM_NEXT_SGL);
1116 config_nand_single_cw_page_read(struct qcom_nand_controller *nandc,
1119 config_nand_page_read(nandc);
1120 config_nand_cw_read(nandc, use_ecc);
1127 static void config_nand_page_write(struct qcom_nand_controller *nandc)
1129 write_reg_dma(nandc, NAND_ADDR0, 2, 0);
1130 write_reg_dma(nandc, NAND_DEV0_CFG0, 3, 0);
1131 write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1,
1139 static void config_nand_cw_write(struct qcom_nand_controller *nandc)
1141 write_reg_dma(nandc, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL);
1142 write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
1144 read_reg_dma(nandc, NAND_FLASH_STATUS, 1, NAND_BAM_NEXT_SGL);
1146 write_reg_dma(nandc, NAND_FLASH_STATUS, 1, 0);
1147 write_reg_dma(nandc, NAND_READ_STATUS, 1, NAND_BAM_NEXT_SGL);
1159 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
1166 nandc_set_reg(nandc, NAND_FLASH_CMD, OP_PAGE_READ | PAGE_ACC | LAST_PAGE);
1167 nandc_set_reg(nandc, NAND_ADDR0, 0);
1168 nandc_set_reg(nandc, NAND_ADDR1, 0);
1169 nandc_set_reg(nandc, NAND_DEV0_CFG0, 0 << CW_PER_PAGE
1173 nandc_set_reg(nandc, NAND_DEV0_CFG1, 7 << NAND_RECOVERY_CYCLES
1180 nandc_set_reg(nandc, NAND_EBI2_ECC_BUF_CFG, 1 << ECC_CFG_ECC_DISABLE);
1183 nandc_set_reg(nandc, NAND_DEV_CMD_VLD,
1184 (nandc->vld & ~READ_START_VLD));
1185 nandc_set_reg(nandc, NAND_DEV_CMD1,
1186 (nandc->cmd1 & ~(0xFF << READ_ADDR))
1189 nandc_set_reg(nandc, NAND_EXEC_CMD, 1);
1191 nandc_set_reg(nandc, NAND_DEV_CMD1_RESTORE, nandc->cmd1);
1192 nandc_set_reg(nandc, NAND_DEV_CMD_VLD_RESTORE, nandc->vld);
1193 nandc_set_read_loc(nandc, 0, 0, 512, 1);
1195 write_reg_dma(nandc, NAND_DEV_CMD_VLD, 1, 0);
1196 write_reg_dma(nandc, NAND_DEV_CMD1, 1, NAND_BAM_NEXT_SGL);
1198 nandc->buf_count = 512;
1199 memset(nandc->data_buffer, 0xff, nandc->buf_count);
1201 config_nand_single_cw_page_read(nandc, false);
1203 read_data_dma(nandc, FLASH_BUF_ACC, nandc->data_buffer,
1204 nandc->buf_count, 0);
1207 write_reg_dma(nandc, NAND_DEV_CMD1_RESTORE, 1, 0);
1208 write_reg_dma(nandc, NAND_DEV_CMD_VLD_RESTORE, 1, NAND_BAM_NEXT_SGL);
1217 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
1219 nandc_set_reg(nandc, NAND_FLASH_CMD,
1221 nandc_set_reg(nandc, NAND_ADDR0, page_addr);
1222 nandc_set_reg(nandc, NAND_ADDR1, 0);
1223 nandc_set_reg(nandc, NAND_DEV0_CFG0,
1225 nandc_set_reg(nandc, NAND_DEV0_CFG1, host->cfg1_raw);
1226 nandc_set_reg(nandc, NAND_EXEC_CMD, 1);
1227 nandc_set_reg(nandc, NAND_FLASH_STATUS, host->clrflashstatus);
1228 nandc_set_reg(nandc, NAND_READ_STATUS, host->clrreadstatus);
1230 write_reg_dma(nandc, NAND_FLASH_CMD, 3, NAND_BAM_NEXT_SGL);
1231 write_reg_dma(nandc, NAND_DEV0_CFG0, 2, NAND_BAM_NEXT_SGL);
1232 write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
1234 read_reg_dma(nandc, NAND_FLASH_STATUS, 1, NAND_BAM_NEXT_SGL);
1236 write_reg_dma(nandc, NAND_FLASH_STATUS, 1, 0);
1237 write_reg_dma(nandc, NAND_READ_STATUS, 1, NAND_BAM_NEXT_SGL);
1246 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
1251 nandc_set_reg(nandc, NAND_FLASH_CMD, OP_FETCH_ID);
1252 nandc_set_reg(nandc, NAND_ADDR0, column);
1253 nandc_set_reg(nandc, NAND_ADDR1, 0);
1254 nandc_set_reg(nandc, NAND_FLASH_CHIP_SELECT,
1255 nandc->props->is_bam ? 0 : DM_EN);
1256 nandc_set_reg(nandc, NAND_EXEC_CMD, 1);
1258 write_reg_dma(nandc, NAND_FLASH_CMD, 4, NAND_BAM_NEXT_SGL);
1259 write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
1261 read_reg_dma(nandc, NAND_READ_ID, 1, NAND_BAM_NEXT_SGL);
1270 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
1272 nandc_set_reg(nandc, NAND_FLASH_CMD, OP_RESET_DEVICE);
1273 nandc_set_reg(nandc, NAND_EXEC_CMD, 1);
1275 write_reg_dma(nandc, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL);
1276 write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
1278 read_reg_dma(nandc, NAND_FLASH_STATUS, 1, NAND_BAM_NEXT_SGL);
1284 static int submit_descs(struct qcom_nand_controller *nandc)
1288 struct bam_transaction *bam_txn = nandc->bam_txn;
1291 if (nandc->props->is_bam) {
1293 r = prepare_bam_async_desc(nandc, nandc->rx_chan, 0);
1299 r = prepare_bam_async_desc(nandc, nandc->tx_chan,
1306 r = prepare_bam_async_desc(nandc, nandc->cmd_chan,
1313 list_for_each_entry(desc, &nandc->desc_list, node)
1316 if (nandc->props->is_bam) {
1325 dma_async_issue_pending(nandc->tx_chan);
1326 dma_async_issue_pending(nandc->rx_chan);
1327 dma_async_issue_pending(nandc->cmd_chan);
1333 if (dma_sync_wait(nandc->chan, cookie) != DMA_COMPLETE)
1340 static void free_descs(struct qcom_nand_controller *nandc)
1344 list_for_each_entry_safe(desc, n, &nandc->desc_list, node) {
1347 if (nandc->props->is_bam)
1348 dma_unmap_sg(nandc->dev, desc->bam_sgl,
1351 dma_unmap_sg(nandc->dev, &desc->adm_sgl, 1,
1359 static void clear_read_regs(struct qcom_nand_controller *nandc)
1361 nandc->reg_read_pos = 0;
1362 nandc_read_buffer_sync(nandc, false);
1368 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
1370 nandc->buf_count = 0;
1371 nandc->buf_start = 0;
1375 clear_read_regs(nandc);
1379 clear_bam_transaction(nandc);
1390 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
1396 nandc_read_buffer_sync(nandc, true);
1399 u32 flash_status = le32_to_cpu(nandc->reg_read_buf[i]);
1414 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
1418 nandc_read_buffer_sync(nandc, true);
1419 memcpy(nandc->data_buffer, nandc->reg_read_buf,
1420 nandc->buf_count);
1442 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
1455 nandc->buf_count = 4;
1492 dev_err(nandc->dev, "failure executing command %d\n",
1494 free_descs(nandc);
1499 ret = submit_descs(nandc);
1501 dev_err(nandc->dev,
1506 free_descs(nandc);
1569 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
1572 nandc_read_buffer_sync(nandc, true);
1575 u32 flash = le32_to_cpu(nandc->reg_read_buf[i]);
1590 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
1598 clear_bam_transaction(nandc);
1601 config_nand_page_read(nandc);
1616 if (nandc->props->is_bam) {
1617 nandc_set_read_loc(nandc, 0, read_loc, data_size1, 0);
1620 nandc_set_read_loc(nandc, 1, read_loc, oob_size1, 0);
1623 nandc_set_read_loc(nandc, 2, read_loc, data_size2, 0);
1626 nandc_set_read_loc(nandc, 3, read_loc, oob_size2, 1);
1629 config_nand_cw_read(nandc, false);
1631 read_data_dma(nandc, reg_off, data_buf, data_size1, 0);
1634 read_data_dma(nandc, reg_off, oob_buf, oob_size1, 0);
1637 read_data_dma(nandc, reg_off, data_buf + data_size1, data_size2, 0);
1640 read_data_dma(nandc, reg_off, oob_buf + oob_size1, oob_size2, 0);
1642 ret = submit_descs(nandc);
1643 free_descs(nandc);
1645 dev_err(nandc->dev, "failure to read raw cw %d\n", cw);
1731 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
1740 buf = (struct read_stats *)nandc->reg_read_buf;
1741 nandc_read_buffer_sync(nandc, true);
1835 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
1840 config_nand_page_read(nandc);
1855 if (nandc->props->is_bam) {
1857 nandc_set_read_loc(nandc, 0, 0, data_size, 0);
1858 nandc_set_read_loc(nandc, 1, data_size,
1861 nandc_set_read_loc(nandc, 0, 0, data_size, 1);
1863 nandc_set_read_loc(nandc, 0, data_size,
1868 config_nand_cw_read(nandc, true);
1871 read_data_dma(nandc, FLASH_BUF_ACC, data_buf,
1887 read_data_dma(nandc, FLASH_BUF_ACC + data_size,
1897 ret = submit_descs(nandc);
1898 free_descs(nandc);
1901 dev_err(nandc->dev, "failure to read page/oob\n");
1915 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
1920 clear_read_regs(nandc);
1925 memset(nandc->data_buffer, 0xff, size);
1930 config_nand_single_cw_page_read(nandc, host->use_ecc);
1932 read_data_dma(nandc, FLASH_BUF_ACC, nandc->data_buffer, size, 0);
1934 ret = submit_descs(nandc);
1936 dev_err(nandc->dev, "failed to copy last codeword\n");
1938 free_descs(nandc);
1948 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
1955 clear_bam_transaction(nandc);
1987 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
1990 clear_read_regs(nandc);
1991 clear_bam_transaction(nandc);
2005 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
2012 clear_read_regs(nandc);
2013 clear_bam_transaction(nandc);
2020 config_nand_page_write(nandc);
2035 write_data_dma(nandc, FLASH_BUF_ACC, data_buf, data_size,
2048 write_data_dma(nandc, FLASH_BUF_ACC + data_size,
2052 config_nand_cw_write(nandc);
2058 ret = submit_descs(nandc);
2060 dev_err(nandc->dev, "failure to write page\n");
2062 free_descs(nandc);
2077 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
2083 clear_read_regs(nandc);
2084 clear_bam_transaction(nandc);
2091 config_nand_page_write(nandc);
2110 write_data_dma(nandc, reg_off, data_buf, data_size1,
2115 write_data_dma(nandc, reg_off, oob_buf, oob_size1,
2120 write_data_dma(nandc, reg_off, data_buf, data_size2,
2125 write_data_dma(nandc, reg_off, oob_buf, oob_size2, 0);
2128 config_nand_cw_write(nandc);
2131 ret = submit_descs(nandc);
2133 dev_err(nandc->dev, "failure to write raw page\n");
2135 free_descs(nandc);
2154 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
2161 clear_bam_transaction(nandc);
2167 memset(nandc->data_buffer, 0xff, host->cw_data);
2169 mtd_ooblayout_get_databytes(mtd, nandc->data_buffer + data_size, oob,
2175 config_nand_page_write(nandc);
2176 write_data_dma(nandc, FLASH_BUF_ACC,
2177 nandc->data_buffer, data_size + oob_size, 0);
2178 config_nand_cw_write(nandc);
2180 ret = submit_descs(nandc);
2182 free_descs(nandc);
2185 dev_err(nandc->dev, "failure to write oob\n");
2196 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
2210 clear_bam_transaction(nandc);
2216 dev_warn(nandc->dev, "error when trying to read BBM\n");
2222 bad = nandc->data_buffer[bbpos] != 0xff;
2225 bad = bad || (nandc->data_buffer[bbpos + 1] != 0xff);
2233 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
2237 clear_read_regs(nandc);
2238 clear_bam_transaction(nandc);
2245 memset(nandc->data_buffer, 0x00, host->cw_size);
2254 config_nand_page_write(nandc);
2255 write_data_dma(nandc, FLASH_BUF_ACC,
2256 nandc->data_buffer, host->cw_size, 0);
2257 config_nand_cw_write(nandc);
2259 ret = submit_descs(nandc);
2261 free_descs(nandc);
2264 dev_err(nandc->dev, "failure to update BBM\n");
2280 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
2281 u8 *buf = nandc->data_buffer;
2292 if (nandc->buf_start < nandc->buf_count)
2293 ret = buf[nandc->buf_start++];
2300 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
2301 int real_len = min_t(size_t, len, nandc->buf_count - nandc->buf_start);
2303 memcpy(buf, nandc->data_buffer + nandc->buf_start, real_len);
2304 nandc->buf_start += real_len;
2310 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
2311 int real_len = min_t(size_t, len, nandc->buf_count - nandc->buf_start);
2313 memcpy(nandc->data_buffer + nandc->buf_start, buf, real_len);
2315 nandc->buf_start += real_len;
2321 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
2326 dev_warn(nandc->dev, "invalid chip select\n");
2470 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
2487 dev_err(nandc->dev, "No valid ECC settings possible\n");
2511 if (nandc->props->ecc_modes & ECC_BCH_4BIT) {
2558 nandc->max_cwperpage = max_t(unsigned int, nandc->max_cwperpage,
2616 nandc->regs->erased_cw_detect_cfg_clr =
2618 nandc->regs->erased_cw_detect_cfg_set =
2621 dev_dbg(nandc->dev,
2634 static void qcom_nandc_unalloc(struct qcom_nand_controller *nandc)
2636 if (nandc->props->is_bam) {
2637 if (!dma_mapping_error(nandc->dev, nandc->reg_read_dma))
2638 dma_unmap_single(nandc->dev, nandc->reg_read_dma,
2640 sizeof(*nandc->reg_read_buf),
2643 if (nandc->tx_chan)
2644 dma_release_channel(nandc->tx_chan);
2646 if (nandc->rx_chan)
2647 dma_release_channel(nandc->rx_chan);
2649 if (nandc->cmd_chan)
2650 dma_release_channel(nandc->cmd_chan);
2652 if (nandc->chan)
2653 dma_release_channel(nandc->chan);
2657 static int qcom_nandc_alloc(struct qcom_nand_controller *nandc)
2661 ret = dma_set_coherent_mask(nandc->dev, DMA_BIT_MASK(32));
2663 dev_err(nandc->dev, "failed to set DMA mask\n");
2673 nandc->buf_size = 532;
2675 nandc->data_buffer = devm_kzalloc(nandc->dev, nandc->buf_size,
2677 if (!nandc->data_buffer)
2680 nandc->regs = devm_kzalloc(nandc->dev, sizeof(*nandc->regs),
2682 if (!nandc->regs)
2685 nandc->reg_read_buf = devm_kcalloc(nandc->dev,
2686 MAX_REG_RD, sizeof(*nandc->reg_read_buf),
2688 if (!nandc->reg_read_buf)
2691 if (nandc->props->is_bam) {
2692 nandc->reg_read_dma =
2693 dma_map_single(nandc->dev, nandc->reg_read_buf,
2695 sizeof(*nandc->reg_read_buf),
2697 if (dma_mapping_error(nandc->dev, nandc->reg_read_dma)) {
2698 dev_err(nandc->dev, "failed to DMA MAP reg buffer\n");
2702 nandc->tx_chan = dma_request_chan(nandc->dev, "tx");
2703 if (IS_ERR(nandc->tx_chan)) {
2704 ret = PTR_ERR(nandc->tx_chan);
2705 nandc->tx_chan = NULL;
2706 dev_err_probe(nandc->dev, ret,
2711 nandc->rx_chan = dma_request_chan(nandc->dev, "rx");
2712 if (IS_ERR(nandc->rx_chan)) {
2713 ret = PTR_ERR(nandc->rx_chan);
2714 nandc->rx_chan = NULL;
2715 dev_err_probe(nandc->dev, ret,
2720 nandc->cmd_chan = dma_request_chan(nandc->dev, "cmd");
2721 if (IS_ERR(nandc->cmd_chan)) {
2722 ret = PTR_ERR(nandc->cmd_chan);
2723 nandc->cmd_chan = NULL;
2724 dev_err_probe(nandc->dev, ret,
2735 nandc->max_cwperpage = 1;
2736 nandc->bam_txn = alloc_bam_transaction(nandc);
2737 if (!nandc->bam_txn) {
2738 dev_err(nandc->dev,
2744 nandc->chan = dma_request_chan(nandc->dev, "rxtx");
2745 if (IS_ERR(nandc->chan)) {
2746 ret = PTR_ERR(nandc->chan);
2747 nandc->chan = NULL;
2748 dev_err_probe(nandc->dev, ret,
2754 INIT_LIST_HEAD(&nandc->desc_list);
2755 INIT_LIST_HEAD(&nandc->host_list);
2757 nand_controller_init(&nandc->controller);
2758 nandc->controller.ops = &qcom_nandc_ops;
2762 qcom_nandc_unalloc(nandc);
2767 static int qcom_nandc_setup(struct qcom_nand_controller *nandc)
2772 if (!nandc->props->is_qpic)
2773 nandc_write(nandc, SFLASHC_BURST_CFG, 0);
2774 nandc_write(nandc, dev_cmd_reg_addr(nandc, NAND_DEV_CMD_VLD),
2778 if (nandc->props->is_bam) {
2779 nand_ctrl = nandc_read(nandc, NAND_CTRL);
2789 nandc_write(nandc, NAND_CTRL, nand_ctrl | BAM_MODE_EN);
2791 nandc_write(nandc, NAND_FLASH_CHIP_SELECT, DM_EN);
2795 nandc->cmd1 = nandc_read(nandc, dev_cmd_reg_addr(nandc, NAND_DEV_CMD1));
2796 nandc->vld = NAND_DEV_CMD_VLD_VAL;
2801 static int qcom_nand_host_init_and_register(struct qcom_nand_controller *nandc,
2807 struct device *dev = nandc->dev;
2843 chip->controller = &nandc->controller;
2854 if (nandc->props->is_bam) {
2855 free_bam_transaction(nandc);
2856 nandc->bam_txn = alloc_bam_transaction(nandc);
2857 if (!nandc->bam_txn) {
2858 dev_err(nandc->dev,
2871 static int qcom_probe_nand_devices(struct qcom_nand_controller *nandc)
2873 struct device *dev = nandc->dev;
2885 ret = qcom_nand_host_init_and_register(nandc, host, child);
2891 list_add_tail(&host->node, &nandc->host_list);
2900 struct qcom_nand_controller *nandc = platform_get_drvdata(pdev);
2901 struct device_node *np = nandc->dev->of_node;
2904 if (!nandc->props->is_bam) {
2906 &nandc->cmd_crci);
2908 dev_err(nandc->dev, "command CRCI unspecified\n");
2913 &nandc->data_crci);
2915 dev_err(nandc->dev, "data CRCI unspecified\n");
2925 struct qcom_nand_controller *nandc;
2931 nandc = devm_kzalloc(&pdev->dev, sizeof(*nandc), GFP_KERNEL);
2932 if (!nandc)
2935 platform_set_drvdata(pdev, nandc);
2936 nandc->dev = dev;
2944 nandc->props = dev_data;
2946 nandc->core_clk = devm_clk_get(dev, "core");
2947 if (IS_ERR(nandc->core_clk))
2948 return PTR_ERR(nandc->core_clk);
2950 nandc->aon_clk = devm_clk_get(dev, "aon");
2951 if (IS_ERR(nandc->aon_clk))
2952 return PTR_ERR(nandc->aon_clk);
2959 nandc->base = devm_ioremap_resource(dev, res);
2960 if (IS_ERR(nandc->base))
2961 return PTR_ERR(nandc->base);
2963 nandc->base_phys = res->start;
2964 nandc->base_dma = dma_map_resource(dev, res->start,
2967 if (!nandc->base_dma)
2970 ret = clk_prepare_enable(nandc->core_clk);
2974 ret = clk_prepare_enable(nandc->aon_clk);
2978 ret = qcom_nandc_alloc(nandc);
2982 ret = qcom_nandc_setup(nandc);
2986 ret = qcom_probe_nand_devices(nandc);
2993 qcom_nandc_unalloc(nandc);
2995 clk_disable_unprepare(nandc->aon_clk);
2997 clk_disable_unprepare(nandc->core_clk);
2999 dma_unmap_resource(dev, nandc->base_dma, resource_size(res),
3006 struct qcom_nand_controller *nandc = platform_get_drvdata(pdev);
3012 list_for_each_entry(host, &nandc->host_list, node) {
3019 qcom_nandc_unalloc(nandc);
3021 clk_disable_unprepare(nandc->aon_clk);
3022 clk_disable_unprepare(nandc->core_clk);
3024 dma_unmap_resource(&pdev->dev, nandc->base_dma, resource_size(res),
3073 .name = "qcom-nandc",