Lines Matching refs:info
190 unsigned int u32_count, int is_write, struct omap_nand_info *info)
197 if (readl(info->reg.gpmc_prefetch_control))
201 writel(u32_count, info->reg.gpmc_prefetch_config2);
209 writel(val, info->reg.gpmc_prefetch_config1);
212 writel(0x1, info->reg.gpmc_prefetch_control);
220 static int omap_prefetch_reset(int cs, struct omap_nand_info *info)
225 config1 = readl(info->reg.gpmc_prefetch_config1);
230 writel(0x0, info->reg.gpmc_prefetch_control);
233 writel(0x0, info->reg.gpmc_prefetch_config1);
251 struct omap_nand_info *info = mtd_to_omap(nand_to_mtd(chip));
255 writeb(cmd, info->reg.gpmc_nand_command);
258 writeb(cmd, info->reg.gpmc_nand_address);
261 writeb(cmd, info->reg.gpmc_nand_data);
286 struct omap_nand_info *info = mtd_to_omap(mtd);
291 iowrite8(*p++, info->nand.legacy.IO_ADDR_W);
294 status = info->ops->nand_writebuffer_empty();
320 struct omap_nand_info *info = mtd_to_omap(mtd);
327 iowrite16(*p++, info->nand.legacy.IO_ADDR_W);
330 status = info->ops->nand_writebuffer_empty();
344 struct omap_nand_info *info = mtd_to_omap(mtd);
351 if (info->nand.options & NAND_BUSWIDTH_16)
360 ret = omap_prefetch_enable(info->gpmc_cs,
361 PREFETCH_FIFOTHRESHOLD_MAX, 0x0, len, 0x0, info);
364 if (info->nand.options & NAND_BUSWIDTH_16)
370 r_count = readl(info->reg.gpmc_prefetch_status);
373 ioread32_rep(info->nand.legacy.IO_ADDR_R, p, r_count);
378 omap_prefetch_reset(info->gpmc_cs, info);
392 struct omap_nand_info *info = mtd_to_omap(mtd);
401 writeb(*buf, info->nand.legacy.IO_ADDR_W);
407 ret = omap_prefetch_enable(info->gpmc_cs,
408 PREFETCH_FIFOTHRESHOLD_MAX, 0x0, len, 0x1, info);
411 if (info->nand.options & NAND_BUSWIDTH_16)
417 w_count = readl(info->reg.gpmc_prefetch_status);
421 iowrite16(*p++, info->nand.legacy.IO_ADDR_W);
429 val = readl(info->reg.gpmc_prefetch_status);
434 omap_prefetch_reset(info->gpmc_cs, info);
457 struct omap_nand_info *info = mtd_to_omap(mtd);
471 n = dma_map_sg(info->dma->device->dev, &sg, 1, dir);
473 dev_err(&info->pdev->dev,
478 tx = dmaengine_prep_slave_sg(info->dma, &sg, n,
485 tx->callback_param = &info->comp;
488 init_completion(&info->comp);
491 dma_async_issue_pending(info->dma);
494 ret = omap_prefetch_enable(info->gpmc_cs,
495 PREFETCH_FIFOTHRESHOLD_MAX, 0x1, len, is_write, info);
500 wait_for_completion(&info->comp);
506 val = readl(info->reg.gpmc_prefetch_status);
511 omap_prefetch_reset(info->gpmc_cs, info);
513 dma_unmap_sg(info->dma->device->dev, &sg, 1, dir);
517 dma_unmap_sg(info->dma->device->dev, &sg, 1, dir);
519 if (info->nand.options & NAND_BUSWIDTH_16)
571 struct omap_nand_info *info = (struct omap_nand_info *) dev;
574 bytes = readl(info->reg.gpmc_prefetch_status);
577 if (info->iomode == OMAP_NAND_IO_WRITE) { /* checks for write io */
578 if (this_irq == info->gpmc_irq_count)
581 if (info->buf_len && (info->buf_len < bytes))
582 bytes = info->buf_len;
583 else if (!info->buf_len)
585 iowrite32_rep(info->nand.legacy.IO_ADDR_W, (u32 *)info->buf,
587 info->buf = info->buf + bytes;
588 info->buf_len -= bytes;
591 ioread32_rep(info->nand.legacy.IO_ADDR_R, (u32 *)info->buf,
593 info->buf = info->buf + bytes;
595 if (this_irq == info->gpmc_irq_count)
602 complete(&info->comp);
604 disable_irq_nosync(info->gpmc_irq_fifo);
605 disable_irq_nosync(info->gpmc_irq_count);
620 struct omap_nand_info *info = mtd_to_omap(mtd);
628 info->iomode = OMAP_NAND_IO_READ;
629 info->buf = buf;
630 init_completion(&info->comp);
633 ret = omap_prefetch_enable(info->gpmc_cs,
634 PREFETCH_FIFOTHRESHOLD_MAX/2, 0x0, len, 0x0, info);
639 info->buf_len = len;
641 enable_irq(info->gpmc_irq_count);
642 enable_irq(info->gpmc_irq_fifo);
645 wait_for_completion(&info->comp);
648 omap_prefetch_reset(info->gpmc_cs, info);
652 if (info->nand.options & NAND_BUSWIDTH_16)
668 struct omap_nand_info *info = mtd_to_omap(mtd);
678 info->iomode = OMAP_NAND_IO_WRITE;
679 info->buf = (u_char *) buf;
680 init_completion(&info->comp);
683 ret = omap_prefetch_enable(info->gpmc_cs,
684 (PREFETCH_FIFOTHRESHOLD_MAX * 3) / 8, 0x0, len, 0x1, info);
689 info->buf_len = len;
691 enable_irq(info->gpmc_irq_count);
692 enable_irq(info->gpmc_irq_fifo);
695 wait_for_completion(&info->comp);
701 val = readl(info->reg.gpmc_prefetch_status);
707 omap_prefetch_reset(info->gpmc_cs, info);
711 if (info->nand.options & NAND_BUSWIDTH_16)
882 struct omap_nand_info *info = mtd_to_omap(nand_to_mtd(chip));
887 if (info->nand.ecc.engine_type == NAND_ECC_ENGINE_TYPE_ON_HOST &&
888 info->nand.ecc.size == 2048)
923 struct omap_nand_info *info = mtd_to_omap(nand_to_mtd(chip));
926 val = readl(info->reg.gpmc_ecc_config);
927 if (((val >> ECC_CONFIG_CS_SHIFT) & CS_MASK) != info->gpmc_cs)
931 val = readl(info->reg.gpmc_ecc1_result);
947 struct omap_nand_info *info = mtd_to_omap(nand_to_mtd(chip));
953 writel(val, info->reg.gpmc_ecc_control);
956 val = ((((info->nand.ecc.size >> 1) - 1) << ECCSIZE1_SHIFT) |
958 writel(val, info->reg.gpmc_ecc_size_config);
963 writel(ECCCLEAR | ECC1, info->reg.gpmc_ecc_control);
966 writel(ECCCLEAR, info->reg.gpmc_ecc_control);
969 dev_info(&info->pdev->dev,
975 val = (dev_width << 7) | (info->gpmc_cs << 1) | (0x1);
976 writel(val, info->reg.gpmc_ecc_config);
992 struct omap_nand_info *info = mtd_to_omap(nand_to_mtd(this));
998 writeb(NAND_CMD_STATUS & 0xFF, info->reg.gpmc_nand_command);
1000 status = readb(info->reg.gpmc_nand_data);
1006 status = readb(info->reg.gpmc_nand_data);
1018 struct omap_nand_info *info = mtd_to_omap(nand_to_mtd(chip));
1020 return gpiod_get_value(info->ready_gpiod);
1039 struct omap_nand_info *info = mtd_to_omap(nand_to_mtd(chip));
1040 enum omap_ecc ecc_opt = info->ecc_opt;
1103 writel(ECC1, info->reg.gpmc_ecc_control);
1107 writel(val, info->reg.gpmc_ecc_size_config);
1117 (info->gpmc_cs << 1) | /* ECC CS */
1120 writel(val, info->reg.gpmc_ecc_config);
1123 writel(ECCCLEAR | ECC1, info->reg.gpmc_ecc_control);
1143 struct omap_nand_info *info = mtd_to_omap(mtd);
1144 int eccbytes = info->nand.ecc.bytes;
1145 struct gpmc_nand_regs *gpmc_regs = &info->reg;
1152 switch (info->ecc_opt) {
1226 switch (info->ecc_opt) {
1285 struct omap_nand_info *info = mtd_to_omap(mtd);
1286 int eccbytes = info->nand.ecc.bytes;
1290 nsectors = ((readl(info->reg.gpmc_ecc_config) >> 4) & 0x7) + 1;
1306 * @info: omap_nand_info
1313 struct omap_nand_info *info)
1317 for (i = 0; i < info->nand.ecc.size; i++) {
1319 if (flip_bits > info->nand.ecc.strength)
1323 for (i = 0; i < info->nand.ecc.bytes - 1; i++) {
1325 if (flip_bits > info->nand.ecc.strength)
1334 memset(data, 0xFF, info->nand.ecc.size);
1335 memset(oob, 0xFF, info->nand.ecc.bytes);
1355 struct omap_nand_info *info = mtd_to_omap(nand_to_mtd(chip));
1356 struct nand_ecc_ctrl *ecc = &info->nand.ecc;
1357 int eccsteps = info->nand.ecc.steps;
1370 switch (info->ecc_opt) {
1386 dev_err(&info->pdev->dev, "invalid driver configuration\n");
1415 buf = &data[info->nand.ecc.size * i];
1422 buf, read_ecc, info);
1452 elm_decode_bch_error_page(info->elm_dev, ecc_vec, err_vec);
1457 dev_err(&info->pdev->dev,
1462 switch (info->ecc_opt) {
1495 dev_err(&info->pdev->dev,
1516 * @chip: nand chip info structure
1554 * @chip: nand chip info structure
1620 * @chip: nand chip info structure
1679 static bool is_elm_present(struct omap_nand_info *info,
1686 dev_err(&info->pdev->dev, "ELM devicetree node not found\n");
1692 dev_err(&info->pdev->dev, "ELM device not found\n");
1696 info->elm_dev = &pdev->dev;
1700 static bool omap2_nand_ecc_check(struct omap_nand_info *info)
1704 switch (info->ecc_opt) {
1726 dev_err(&info->pdev->dev,
1731 dev_err(&info->pdev->dev,
1735 if (ecc_needs_elm && !is_elm_present(info, info->elm_of_node)) {
1736 dev_err(&info->pdev->dev, "ELM not available\n");
1750 static int omap_get_dt_info(struct device *dev, struct omap_nand_info *info)
1762 info->gpmc_cs = cs;
1765 info->elm_of_node = of_parse_phandle(child, "ti,elm-id", 0);
1766 if (!info->elm_of_node) {
1767 info->elm_of_node = of_parse_phandle(child, "elm_id", 0);
1768 if (!info->elm_of_node)
1779 info->ecc_opt = OMAP_ECC_HAM1_CODE_SW;
1782 info->ecc_opt = OMAP_ECC_HAM1_CODE_HW;
1784 if (info->elm_of_node)
1785 info->ecc_opt = OMAP_ECC_BCH4_CODE_HW;
1787 info->ecc_opt = OMAP_ECC_BCH4_CODE_HW_DETECTION_SW;
1789 if (info->elm_of_node)
1790 info->ecc_opt = OMAP_ECC_BCH8_CODE_HW;
1792 info->ecc_opt = OMAP_ECC_BCH8_CODE_HW_DETECTION_SW;
1794 info->ecc_opt = OMAP_ECC_BCH16_CODE_HW;
1804 info->xfer_type = i;
1819 struct omap_nand_info *info = mtd_to_omap(mtd);
1820 struct nand_chip *chip = &info->nand;
1823 if (info->ecc_opt == OMAP_ECC_HAM1_CODE_HW &&
1839 struct omap_nand_info *info = mtd_to_omap(mtd);
1840 struct nand_chip *chip = &info->nand;
1843 if (info->ecc_opt == OMAP_ECC_HAM1_CODE_HW &&
1915 struct omap_nand_info *info = mtd_to_omap(mtd);
1916 struct device *dev = &info->pdev->dev;
1928 switch (info->xfer_type) {
1941 info->dma = dma_request_chan(dev->parent, "rxtx");
1943 if (IS_ERR(info->dma)) {
1945 return PTR_ERR(info->dma);
1950 cfg.src_addr = info->phys_base;
1951 cfg.dst_addr = info->phys_base;
1956 err = dmaengine_slave_config(info->dma, &cfg);
1969 info->gpmc_irq_fifo = platform_get_irq(info->pdev, 0);
1970 if (info->gpmc_irq_fifo <= 0)
1972 err = devm_request_irq(dev, info->gpmc_irq_fifo,
1974 "gpmc-nand-fifo", info);
1977 info->gpmc_irq_fifo, err);
1978 info->gpmc_irq_fifo = 0;
1982 info->gpmc_irq_count = platform_get_irq(info->pdev, 1);
1983 if (info->gpmc_irq_count <= 0)
1985 err = devm_request_irq(dev, info->gpmc_irq_count,
1987 "gpmc-nand-count", info);
1990 info->gpmc_irq_count, err);
1991 info->gpmc_irq_count = 0;
2001 dev_err(dev, "xfer_type %d not supported!\n", info->xfer_type);
2005 if (!omap2_nand_ecc_check(info))
2012 if (info->ecc_opt == OMAP_ECC_HAM1_CODE_SW) {
2019 switch (info->ecc_opt) {
2072 err = elm_config(info->elm_dev, BCH4_ECC,
2114 err = elm_config(info->elm_dev, BCH8_ECC,
2136 err = elm_config(info->elm_dev, BCH16_ECC,
2171 struct omap_nand_info *info;
2178 info = devm_kzalloc(&pdev->dev, sizeof(struct omap_nand_info),
2180 if (!info)
2183 info->pdev = pdev;
2185 err = omap_get_dt_info(dev, info);
2189 info->ops = gpmc_omap_get_nand_ops(&info->reg, info->gpmc_cs);
2190 if (!info->ops) {
2195 nand_chip = &info->nand;
2203 "omap2-nand.%d", info->gpmc_cs);
2215 info->phys_base = res->start;
2228 info->ready_gpiod = devm_gpiod_get_optional(&pdev->dev, "rb",
2230 if (IS_ERR(info->ready_gpiod)) {
2232 return PTR_ERR(info->ready_gpiod);
2242 if (info->ready_gpiod) {
2250 if (info->flash_bbt)
2254 nand_chip->options |= info->devsize & NAND_BUSWIDTH_16;
2272 if (!IS_ERR_OR_NULL(info->dma))
2273 dma_release_channel(info->dma);
2285 struct omap_nand_info *info = mtd_to_omap(mtd);
2292 if (info->dma)
2293 dma_release_channel(info->dma);