Lines Matching defs:ecc
128 int (*read_page)(struct nand_chip *chip, void *buf, void *oob, bool ecc,
672 if (chip->ecc.engine_type != NAND_ECC_ENGINE_TYPE_ON_HOST)
690 if (chip->ecc.engine_type != NAND_ECC_ENGINE_TYPE_ON_HOST)
714 bool ecc, int page)
722 host->devtype_data->enable_hwecc(chip, ecc);
747 if (buf && ecc) {
772 void *oob, bool ecc, int page)
781 host->devtype_data->enable_hwecc(chip, ecc);
856 bool ecc, int page)
861 host->devtype_data->enable_hwecc(chip, ecc);
1010 if (section >= nand_chip->ecc.steps)
1024 if (section > nand_chip->ecc.steps)
1037 if (section < nand_chip->ecc.steps)
1048 .ecc = mxc_v1_ooblayout_ecc,
1056 int stepsize = nand_chip->ecc.bytes == 9 ? 16 : 26;
1058 if (section >= nand_chip->ecc.steps)
1062 oobregion->length = nand_chip->ecc.bytes;
1071 int stepsize = nand_chip->ecc.bytes == 9 ? 16 : 26;
1073 if (section >= nand_chip->ecc.steps)
1093 .ecc = mxc_v2_ooblayout_ecc,
1098 * v2 and v3 type controllers can do 4bit or 8bit ecc depending
1099 * on how much oob the nand chip has. For 8bit ecc we need at least
1120 if (nand_chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_ON_HOST &&
1231 if (nand_chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_ON_HOST)
1307 if (chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_ON_HOST)
1436 * The generic flash bbt descriptors overlap with our ecc
1684 chip->ecc.bytes = host->devtype_data->eccbytes;
1686 chip->ecc.size = 512;
1689 switch (chip->ecc.engine_type) {
1691 chip->ecc.read_page = mxc_nand_read_page;
1692 chip->ecc.read_page_raw = mxc_nand_read_page_raw;
1693 chip->ecc.read_oob = mxc_nand_read_oob;
1694 chip->ecc.write_page = mxc_nand_write_page_ecc;
1695 chip->ecc.write_page_raw = mxc_nand_write_page_raw;
1696 chip->ecc.write_oob = mxc_nand_write_oob;
1721 if (!chip->ecc.bytes) {
1723 chip->ecc.bytes = 18;
1725 chip->ecc.bytes = 9;
1737 if (chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_ON_HOST) {
1739 chip->ecc.strength = 1;
1741 chip->ecc.strength = (host->eccsize == 4) ? 4 : 8;