Lines Matching refs:nfc
217 struct mtk_nfc *nfc = nand_get_controller_data(chip);
219 return nfc->buffer + i * mtk_data_len(chip);
224 struct mtk_nfc *nfc = nand_get_controller_data(chip);
226 return nfc->buffer + i * mtk_data_len(chip) + chip->ecc.size;
229 static inline void nfi_writel(struct mtk_nfc *nfc, u32 val, u32 reg)
231 writel(val, nfc->regs + reg);
234 static inline void nfi_writew(struct mtk_nfc *nfc, u16 val, u32 reg)
236 writew(val, nfc->regs + reg);
239 static inline void nfi_writeb(struct mtk_nfc *nfc, u8 val, u32 reg)
241 writeb(val, nfc->regs + reg);
244 static inline u32 nfi_readl(struct mtk_nfc *nfc, u32 reg)
246 return readl_relaxed(nfc->regs + reg);
249 static inline u16 nfi_readw(struct mtk_nfc *nfc, u32 reg)
251 return readw_relaxed(nfc->regs + reg);
254 static inline u8 nfi_readb(struct mtk_nfc *nfc, u32 reg)
256 return readb_relaxed(nfc->regs + reg);
259 static void mtk_nfc_hw_reset(struct mtk_nfc *nfc)
261 struct device *dev = nfc->dev;
266 nfi_writel(nfc, CON_FIFO_FLUSH | CON_NFI_RST, NFI_CON);
269 ret = readl_poll_timeout(nfc->regs + NFI_MASTER_STA, val,
277 nfi_writel(nfc, CON_FIFO_FLUSH | CON_NFI_RST, NFI_CON);
278 nfi_writew(nfc, STAR_DE, NFI_STRDATA);
281 static int mtk_nfc_send_command(struct mtk_nfc *nfc, u8 command)
283 struct device *dev = nfc->dev;
287 nfi_writel(nfc, command, NFI_CMD);
289 ret = readl_poll_timeout_atomic(nfc->regs + NFI_STA, val,
299 static int mtk_nfc_send_address(struct mtk_nfc *nfc, int addr)
301 struct device *dev = nfc->dev;
305 nfi_writel(nfc, addr, NFI_COLADDR);
306 nfi_writel(nfc, 0, NFI_ROWADDR);
307 nfi_writew(nfc, 1, NFI_ADDRNOB);
309 ret = readl_poll_timeout_atomic(nfc->regs + NFI_STA, val,
323 struct mtk_nfc *nfc = nand_get_controller_data(chip);
357 dev_err(nfc->dev, "invalid page len: %d\n", mtd->writesize);
368 for (i = 0; i < nfc->caps->num_spare_size; i++) {
369 if (nfc->caps->spare_size[i] == spare)
373 if (i == nfc->caps->num_spare_size) {
374 dev_err(nfc->dev, "invalid spare size %d\n", spare);
378 fmt |= i << nfc->caps->pageformat_spare_shift;
382 nfi_writel(nfc, fmt, NFI_PAGEFMT);
384 nfc->ecc_cfg.strength = chip->ecc.strength;
385 nfc->ecc_cfg.len = chip->ecc.size + mtk_nand->fdm.ecc_size;
390 static inline void mtk_nfc_wait_ioready(struct mtk_nfc *nfc)
395 rc = readb_poll_timeout_atomic(nfc->regs + NFI_PIO_DIRDY, val,
398 dev_err(nfc->dev, "data not ready\n");
403 struct mtk_nfc *nfc = nand_get_controller_data(chip);
407 reg = nfi_readl(nfc, NFI_STA) & NFI_FSM_MASK;
409 reg = nfi_readw(nfc, NFI_CNFG);
411 nfi_writew(nfc, reg, NFI_CNFG);
417 reg = (nfc->caps->max_sector << CON_SEC_SHIFT) | CON_BRD;
418 nfi_writel(nfc, reg, NFI_CON);
421 nfi_writew(nfc, STAR_EN, NFI_STRDATA);
424 mtk_nfc_wait_ioready(nfc);
426 return nfi_readb(nfc, NFI_DATAR);
439 struct mtk_nfc *nfc = nand_get_controller_data(chip);
442 reg = nfi_readl(nfc, NFI_STA) & NFI_FSM_MASK;
445 reg = nfi_readw(nfc, NFI_CNFG) | CNFG_BYTE_RW;
446 nfi_writew(nfc, reg, NFI_CNFG);
448 reg = nfc->caps->max_sector << CON_SEC_SHIFT | CON_BWR;
449 nfi_writel(nfc, reg, NFI_CON);
451 nfi_writew(nfc, STAR_EN, NFI_STRDATA);
454 mtk_nfc_wait_ioready(nfc);
455 nfi_writeb(nfc, byte, NFI_DATAW);
469 struct mtk_nfc *nfc = nand_get_controller_data(chip);
475 mtk_nfc_send_command(nfc, instr->ctx.cmd.opcode);
479 mtk_nfc_send_address(nfc, instr->ctx.addr.addrs[i]);
490 return readl_poll_timeout(nfc->regs + NFI_STA, status,
502 struct mtk_nfc *nfc = nand_get_controller_data(nand);
507 nfi_writel(nfc, mtk_nand->sels[cs], NFI_CSEL);
514 struct mtk_nfc *nfc = nand_get_controller_data(chip);
521 mtk_nfc_hw_reset(nfc);
522 nfi_writew(nfc, CNFG_OP_CUST, NFI_CNFG);
537 struct mtk_nfc *nfc = nand_get_controller_data(chip);
549 rate = clk_get_rate(nfc->clk.nfi_clk);
551 rate /= nfc->caps->nfi_clk_div;
618 temp = nfi_readl(nfc, NFI_DEBUG_CON1);
621 nfi_writel(nfc, temp, NFI_DEBUG_CON1);
637 nfi_writel(nfc, trlt, NFI_ACCCON);
644 struct mtk_nfc *nfc = nand_get_controller_data(chip);
648 nfc->ecc_cfg.mode = ECC_DMA_MODE;
649 nfc->ecc_cfg.op = ECC_ENCODE;
651 return mtk_ecc_encode(nfc->ecc, &nfc->ecc_cfg, data, size);
678 struct mtk_nfc *nfc = nand_get_controller_data(chip);
686 memset(nfc->buffer, 0xff, mtd->writesize + mtd->oobsize);
695 mtk_nand->bad_mark.bm_swap(mtd, nfc->buffer, 1);
712 struct mtk_nfc *nfc = nand_get_controller_data(chip);
716 memset(nfc->buffer, 0xff, mtd->writesize + mtd->oobsize);
723 mtk_nand->bad_mark.bm_swap(mtd, nfc->buffer, 1);
732 struct mtk_nfc *nfc = nand_get_controller_data(chip);
741 vall = nfi_readl(nfc, NFI_FDML(i));
742 valm = nfi_readl(nfc, NFI_FDMM(i));
751 struct mtk_nfc *nfc = nand_get_controller_data(chip);
770 nfi_writel(nfc, vall, NFI_FDML(i));
771 nfi_writel(nfc, valm, NFI_FDMM(i));
778 struct mtk_nfc *nfc = nand_get_controller_data(chip);
779 struct device *dev = nfc->dev;
785 ret = dma_mapping_error(nfc->dev, addr);
787 dev_err(nfc->dev, "dma mapping error\n");
791 reg = nfi_readw(nfc, NFI_CNFG) | CNFG_AHB | CNFG_DMA_BURST_EN;
792 nfi_writew(nfc, reg, NFI_CNFG);
794 nfi_writel(nfc, chip->ecc.steps << CON_SEC_SHIFT, NFI_CON);
795 nfi_writel(nfc, lower_32_bits(addr), NFI_STRADDR);
796 nfi_writew(nfc, INTR_AHB_DONE_EN, NFI_INTR_EN);
798 init_completion(&nfc->done);
800 reg = nfi_readl(nfc, NFI_CON) | CON_BWR;
801 nfi_writel(nfc, reg, NFI_CON);
802 nfi_writew(nfc, STAR_EN, NFI_STRDATA);
804 ret = wait_for_completion_timeout(&nfc->done, msecs_to_jiffies(500));
807 nfi_writew(nfc, 0, NFI_INTR_EN);
812 ret = readl_poll_timeout_atomic(nfc->regs + NFI_ADDRCNTR, reg,
820 dma_unmap_single(nfc->dev, addr, len, DMA_TO_DEVICE);
821 nfi_writel(nfc, 0, NFI_CON);
829 struct mtk_nfc *nfc = nand_get_controller_data(chip);
841 reg = nfi_readw(nfc, NFI_CNFG) | CNFG_AUTO_FMT_EN;
842 nfi_writew(nfc, reg | CNFG_HW_ECC_EN, NFI_CNFG);
844 nfc->ecc_cfg.op = ECC_ENCODE;
845 nfc->ecc_cfg.mode = ECC_NFI_MODE;
846 ret = mtk_ecc_enable(nfc->ecc, &nfc->ecc_cfg);
849 reg = nfi_readw(nfc, NFI_CNFG);
851 nfi_writew(nfc, reg, NFI_CNFG);
856 memcpy(nfc->buffer, buf, mtd->writesize);
857 mtk_nand->bad_mark.bm_swap(mtd, nfc->buffer, raw);
858 bufpoi = nfc->buffer;
870 mtk_ecc_disable(nfc->ecc);
888 struct mtk_nfc *nfc = nand_get_controller_data(chip);
891 return mtk_nfc_write_page(mtd, chip, nfc->buffer, pg, 1);
899 struct mtk_nfc *nfc = nand_get_controller_data(chip);
907 return mtk_nfc_write_page(mtd, chip, nfc->buffer, page, 1);
919 struct mtk_nfc *nfc = nand_get_controller_data(chip);
925 rc = nfi_readl(nfc, NFI_STA) & STA_EMP_PAGE;
933 mtk_ecc_get_stats(nfc->ecc, &stats, sectors);
944 struct mtk_nfc *nfc = nand_get_controller_data(chip);
966 addr = dma_map_single(nfc->dev, buf, len, DMA_FROM_DEVICE);
967 rc = dma_mapping_error(nfc->dev, addr);
969 dev_err(nfc->dev, "dma mapping error\n");
974 reg = nfi_readw(nfc, NFI_CNFG);
978 nfi_writew(nfc, reg, NFI_CNFG);
980 nfc->ecc_cfg.mode = ECC_NFI_MODE;
981 nfc->ecc_cfg.sectors = sectors;
982 nfc->ecc_cfg.op = ECC_DECODE;
983 rc = mtk_ecc_enable(nfc->ecc, &nfc->ecc_cfg);
985 dev_err(nfc->dev, "ecc enable\n");
989 nfi_writew(nfc, reg, NFI_CNFG);
990 dma_unmap_single(nfc->dev, addr, len, DMA_FROM_DEVICE);
995 nfi_writew(nfc, reg, NFI_CNFG);
998 nfi_writel(nfc, sectors << CON_SEC_SHIFT, NFI_CON);
999 nfi_writew(nfc, INTR_AHB_DONE_EN, NFI_INTR_EN);
1000 nfi_writel(nfc, lower_32_bits(addr), NFI_STRADDR);
1002 init_completion(&nfc->done);
1003 reg = nfi_readl(nfc, NFI_CON) | CON_BRD;
1004 nfi_writel(nfc, reg, NFI_CON);
1005 nfi_writew(nfc, STAR_EN, NFI_STRDATA);
1007 rc = wait_for_completion_timeout(&nfc->done, msecs_to_jiffies(500));
1009 dev_warn(nfc->dev, "read ahb/dma done timeout\n");
1011 rc = readl_poll_timeout_atomic(nfc->regs + NFI_BYTELEN, reg,
1015 dev_err(nfc->dev, "subpage done timeout\n");
1018 rc = mtk_ecc_wait_done(nfc->ecc, ECC_DECODE);
1024 dma_unmap_single(nfc->dev, addr, len, DMA_FROM_DEVICE);
1029 mtk_ecc_disable(nfc->ecc);
1034 nfi_writel(nfc, 0, NFI_CON);
1059 struct mtk_nfc *nfc = nand_get_controller_data(chip);
1063 memset(nfc->buffer, 0xff, mtd->writesize + mtd->oobsize);
1064 ret = mtk_nfc_read_subpage(mtd, chip, 0, mtd->writesize, nfc->buffer,
1073 mtk_nand->bad_mark.bm_swap(mtd, nfc->buffer, 1);
1088 static inline void mtk_nfc_hw_init(struct mtk_nfc *nfc)
1096 nfi_writew(nfc, 0xf1, NFI_CNRNB);
1097 nfi_writel(nfc, PAGEFMT_8K_16K, NFI_PAGEFMT);
1099 mtk_nfc_hw_reset(nfc);
1101 nfi_readl(nfc, NFI_INTR_STA);
1102 nfi_writel(nfc, 0, NFI_INTR_EN);
1107 struct mtk_nfc *nfc = id;
1110 sta = nfi_readw(nfc, NFI_INTR_STA);
1111 ien = nfi_readw(nfc, NFI_INTR_EN);
1116 nfi_writew(nfc, ~sta & ien, NFI_INTR_EN);
1117 complete(&nfc->done);
1193 struct mtk_nfc *nfc = nand_get_controller_data(nand);
1197 mtk_ecc_get_parity_bits(nfc->ecc), 8);
1224 struct mtk_nfc *nfc = nand_get_controller_data(nand);
1225 const u8 *spare = nfc->caps->spare_size;
1237 for (i = 0; i < nfc->caps->num_spare_size; i++) {
1258 struct mtk_nfc *nfc = nand_get_controller_data(nand);
1280 nfc->caps->max_sector_size > 512) {
1295 free = (nand->ecc.strength * mtk_ecc_get_parity_bits(nfc->ecc)
1307 mtk_ecc_get_parity_bits(nfc->ecc);
1311 mtk_ecc_get_parity_bits(nfc->ecc);
1315 mtk_ecc_adjust_strength(nfc->ecc, &nand->ecc.strength);
1327 struct mtk_nfc *nfc = nand_get_controller_data(chip);
1353 nfc->buffer = devm_kzalloc(dev, len, GFP_KERNEL);
1354 if (!nfc->buffer)
1366 static int mtk_nfc_nand_chip_init(struct device *dev, struct mtk_nfc *nfc,
1404 if (test_and_set_bit(tmp, &nfc->assigned_cs)) {
1413 nand->controller = &nfc->controller;
1416 nand_set_controller_data(nand, nfc);
1441 mtk_nfc_hw_init(nfc);
1454 list_add_tail(&chip->node, &nfc->chips);
1459 static int mtk_nfc_nand_chips_init(struct device *dev, struct mtk_nfc *nfc)
1466 ret = mtk_nfc_nand_chip_init(dev, nfc, nand_np);
1505 .compatible = "mediatek,mt2701-nfc",
1508 .compatible = "mediatek,mt2712-nfc",
1511 .compatible = "mediatek,mt7622-nfc",
1522 struct mtk_nfc *nfc;
1526 nfc = devm_kzalloc(dev, sizeof(*nfc), GFP_KERNEL);
1527 if (!nfc)
1530 nand_controller_init(&nfc->controller);
1531 INIT_LIST_HEAD(&nfc->chips);
1532 nfc->controller.ops = &mtk_nfc_controller_ops;
1535 nfc->ecc = of_mtk_ecc_get(np);
1536 if (IS_ERR(nfc->ecc))
1537 return PTR_ERR(nfc->ecc);
1538 else if (!nfc->ecc)
1541 nfc->caps = of_device_get_match_data(dev);
1542 nfc->dev = dev;
1545 nfc->regs = devm_ioremap_resource(dev, res);
1546 if (IS_ERR(nfc->regs)) {
1547 ret = PTR_ERR(nfc->regs);
1551 nfc->clk.nfi_clk = devm_clk_get(dev, "nfi_clk");
1552 if (IS_ERR(nfc->clk.nfi_clk)) {
1554 ret = PTR_ERR(nfc->clk.nfi_clk);
1558 nfc->clk.pad_clk = devm_clk_get(dev, "pad_clk");
1559 if (IS_ERR(nfc->clk.pad_clk)) {
1561 ret = PTR_ERR(nfc->clk.pad_clk);
1565 ret = mtk_nfc_enable_clk(dev, &nfc->clk);
1575 ret = devm_request_irq(dev, irq, mtk_nfc_irq, 0x0, "mtk-nand", nfc);
1587 platform_set_drvdata(pdev, nfc);
1589 ret = mtk_nfc_nand_chips_init(dev, nfc);
1598 mtk_nfc_disable_clk(&nfc->clk);
1601 mtk_ecc_release(nfc->ecc);
1608 struct mtk_nfc *nfc = platform_get_drvdata(pdev);
1613 while (!list_empty(&nfc->chips)) {
1614 mtk_chip = list_first_entry(&nfc->chips,
1623 mtk_ecc_release(nfc->ecc);
1624 mtk_nfc_disable_clk(&nfc->clk);
1632 struct mtk_nfc *nfc = dev_get_drvdata(dev);
1634 mtk_nfc_disable_clk(&nfc->clk);
1641 struct mtk_nfc *nfc = dev_get_drvdata(dev);
1649 ret = mtk_nfc_enable_clk(dev, &nfc->clk);
1654 list_for_each_entry(chip, &nfc->chips, node) {