Lines Matching refs:ecc
68 /* ecc strength that each IP supports */
119 static inline void mtk_ecc_wait_idle(struct mtk_ecc *ecc,
122 struct device *dev = ecc->dev;
126 ret = readl_poll_timeout_atomic(ecc->regs + ECC_IDLE_REG(op), val,
136 struct mtk_ecc *ecc = id;
139 dec = readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECIRQ_STA])
142 dec = readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECDONE]);
143 if (dec & ecc->sectors) {
148 readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECIRQ_STA]);
149 ecc->sectors = 0;
150 complete(&ecc->done);
155 enc = readl(ecc->regs + ecc->caps->ecc_regs[ECC_ENCIRQ_STA])
158 complete(&ecc->done);
166 static int mtk_ecc_config(struct mtk_ecc *ecc, struct mtk_ecc_config *config)
171 for (i = 0; i < ecc->caps->num_ecc_strength; i++) {
172 if (ecc->caps->ecc_strength[i] == config->strength)
176 if (i == ecc->caps->num_ecc_strength) {
177 dev_err(ecc->dev, "invalid ecc strength %d\n",
188 reg = ecc_bit | (config->mode << ecc->caps->ecc_mode_shift);
190 writel(reg, ecc->regs + ECC_ENCCNFG);
194 ecc->regs + ECC_ENCDIADDR);
199 config->strength * ecc->caps->parity_bits;
201 reg = ecc_bit | (config->mode << ecc->caps->ecc_mode_shift);
204 writel(reg, ecc->regs + ECC_DECCNFG);
207 ecc->sectors = 1 << (config->sectors - 1);
213 void mtk_ecc_get_stats(struct mtk_ecc *ecc, struct mtk_ecc_stats *stats,
224 err = readl(ecc->regs + ECC_DECENUM0 + offset);
225 err = err >> ((i % 4) * ecc->caps->err_shift);
226 err &= ecc->caps->err_mask;
227 if (err == ecc->caps->err_mask) {
241 void mtk_ecc_release(struct mtk_ecc *ecc)
243 clk_disable_unprepare(ecc->clk);
244 put_device(ecc->dev);
248 static void mtk_ecc_hw_init(struct mtk_ecc *ecc)
250 mtk_ecc_wait_idle(ecc, ECC_ENCODE);
251 writew(ECC_OP_DISABLE, ecc->regs + ECC_ENCCON);
253 mtk_ecc_wait_idle(ecc, ECC_DECODE);
254 writel(ECC_OP_DISABLE, ecc->regs + ECC_DECCON);
260 struct mtk_ecc *ecc;
266 ecc = platform_get_drvdata(pdev);
267 if (!ecc) {
272 clk_prepare_enable(ecc->clk);
273 mtk_ecc_hw_init(ecc);
275 return ecc;
280 struct mtk_ecc *ecc = NULL;
283 np = of_parse_phandle(of_node, "ecc-engine", 0);
285 ecc = mtk_ecc_get(np);
289 return ecc;
293 int mtk_ecc_enable(struct mtk_ecc *ecc, struct mtk_ecc_config *config)
299 ret = mutex_lock_interruptible(&ecc->lock);
301 dev_err(ecc->dev, "interrupted when attempting to lock\n");
305 mtk_ecc_wait_idle(ecc, op);
307 ret = mtk_ecc_config(ecc, config);
309 mutex_unlock(&ecc->lock);
314 init_completion(&ecc->done);
317 * For ECC_NFI_MODE, if ecc->caps->pg_irq_sel is 1, then it
318 * means this chip can only generate one ecc irq during page
319 * read / write. If is 0, generate one ecc irq each ecc step.
321 if (ecc->caps->pg_irq_sel && config->mode == ECC_NFI_MODE)
324 writew(reg_val, ecc->regs +
325 ecc->caps->ecc_regs[ECC_ENCIRQ_EN]);
327 writew(reg_val, ecc->regs +
328 ecc->caps->ecc_regs[ECC_DECIRQ_EN]);
331 writew(ECC_OP_ENABLE, ecc->regs + ECC_CTL_REG(op));
337 void mtk_ecc_disable(struct mtk_ecc *ecc)
342 if (readw(ecc->regs + ECC_CTL_REG(op)) != ECC_OP_ENABLE)
346 mtk_ecc_wait_idle(ecc, op);
352 readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECDONE]);
353 writew(0, ecc->regs + ecc->caps->ecc_regs[ECC_DECIRQ_EN]);
355 writew(0, ecc->regs + ecc->caps->ecc_regs[ECC_ENCIRQ_EN]);
358 writew(ECC_OP_DISABLE, ecc->regs + ECC_CTL_REG(op));
360 mutex_unlock(&ecc->lock);
364 int mtk_ecc_wait_done(struct mtk_ecc *ecc, enum mtk_ecc_operation op)
368 ret = wait_for_completion_timeout(&ecc->done, msecs_to_jiffies(500));
370 dev_err(ecc->dev, "%s timeout - interrupt did not arrive)\n",
379 int mtk_ecc_encode(struct mtk_ecc *ecc, struct mtk_ecc_config *config,
386 addr = dma_map_single(ecc->dev, data, bytes, DMA_TO_DEVICE);
387 ret = dma_mapping_error(ecc->dev, addr);
389 dev_err(ecc->dev, "dma mapping error\n");
395 ret = mtk_ecc_enable(ecc, config);
397 dma_unmap_single(ecc->dev, addr, bytes, DMA_TO_DEVICE);
401 ret = mtk_ecc_wait_done(ecc, ECC_ENCODE);
405 mtk_ecc_wait_idle(ecc, ECC_ENCODE);
408 len = (config->strength * ecc->caps->parity_bits + 7) >> 3;
411 __ioread32_copy(ecc->eccdata,
412 ecc->regs + ecc->caps->ecc_regs[ECC_ENCPAR00],
416 memcpy(data + bytes, ecc->eccdata, len);
419 dma_unmap_single(ecc->dev, addr, bytes, DMA_TO_DEVICE);
420 mtk_ecc_disable(ecc);
426 void mtk_ecc_adjust_strength(struct mtk_ecc *ecc, u32 *p)
428 const u8 *ecc_strength = ecc->caps->ecc_strength;
431 for (i = 0; i < ecc->caps->num_ecc_strength; i++) {
441 *p = ecc_strength[ecc->caps->num_ecc_strength - 1];
445 unsigned int mtk_ecc_get_parity_bits(struct mtk_ecc *ecc)
447 return ecc->caps->parity_bits;
486 .compatible = "mediatek,mt2701-ecc",
489 .compatible = "mediatek,mt2712-ecc",
492 .compatible = "mediatek,mt7622-ecc",
501 struct mtk_ecc *ecc;
506 ecc = devm_kzalloc(dev, sizeof(*ecc), GFP_KERNEL);
507 if (!ecc)
510 ecc->caps = of_device_get_match_data(dev);
512 max_eccdata_size = ecc->caps->num_ecc_strength - 1;
513 max_eccdata_size = ecc->caps->ecc_strength[max_eccdata_size];
514 max_eccdata_size = (max_eccdata_size * ecc->caps->parity_bits + 7) >> 3;
516 ecc->eccdata = devm_kzalloc(dev, max_eccdata_size, GFP_KERNEL);
517 if (!ecc->eccdata)
521 ecc->regs = devm_ioremap_resource(dev, res);
522 if (IS_ERR(ecc->regs)) {
523 dev_err(dev, "failed to map regs: %ld\n", PTR_ERR(ecc->regs));
524 return PTR_ERR(ecc->regs);
527 ecc->clk = devm_clk_get(dev, NULL);
528 if (IS_ERR(ecc->clk)) {
529 dev_err(dev, "failed to get clock: %ld\n", PTR_ERR(ecc->clk));
530 return PTR_ERR(ecc->clk);
543 ret = devm_request_irq(dev, irq, mtk_ecc_irq, 0x0, "mtk-ecc", ecc);
549 ecc->dev = dev;
550 mutex_init(&ecc->lock);
551 platform_set_drvdata(pdev, ecc);
560 struct mtk_ecc *ecc = dev_get_drvdata(dev);
562 clk_disable_unprepare(ecc->clk);
569 struct mtk_ecc *ecc = dev_get_drvdata(dev);
572 ret = clk_prepare_enable(ecc->clk);
589 .name = "mtk-ecc",