Lines Matching refs:nfc
227 struct meson_nfc *nfc = nand_get_controller_data(nand);
233 nfc->param.chip_select = meson_chip->sels[chip] ? NAND_CE1 : NAND_CE0;
234 nfc->param.rb_select = nfc->param.chip_select;
235 nfc->timing.twb = meson_chip->twb;
236 nfc->timing.tadl = meson_chip->tadl;
237 nfc->timing.tbers_max = meson_chip->tbers_max;
239 if (nfc->clk_rate != meson_chip->clk_rate) {
240 ret = clk_set_rate(nfc->device_clk, meson_chip->clk_rate);
242 dev_err(nfc->dev, "failed to set clock rate\n");
245 nfc->clk_rate = meson_chip->clk_rate;
247 if (nfc->bus_timing != meson_chip->bus_timing) {
249 writel(value, nfc->reg_base + NFC_REG_CFG);
250 writel((1 << 31), nfc->reg_base + NFC_REG_CMD);
251 nfc->bus_timing = meson_chip->bus_timing;
255 static void meson_nfc_cmd_idle(struct meson_nfc *nfc, u32 time)
257 writel(nfc->param.chip_select | NFC_CMD_IDLE | (time & 0x3ff),
258 nfc->reg_base + NFC_REG_CMD);
261 static void meson_nfc_cmd_seed(struct meson_nfc *nfc, u32 seed)
264 nfc->reg_base + NFC_REG_CMD);
271 struct meson_nfc *nfc = nand_get_controller_data(mtd_to_nand(mtd));
281 writel(cmd, nfc->reg_base + NFC_REG_CMD);
290 writel(cmd, nfc->reg_base + NFC_REG_CMD);
293 static void meson_nfc_drain_cmd(struct meson_nfc *nfc)
306 meson_nfc_cmd_idle(nfc, 0);
307 meson_nfc_cmd_idle(nfc, 0);
310 static int meson_nfc_wait_cmd_finish(struct meson_nfc *nfc,
317 ret = readl_relaxed_poll_timeout(nfc->reg_base + NFC_REG_CMD, cmd_size,
321 dev_err(nfc->dev, "wait for empty CMD FIFO time out\n");
326 static int meson_nfc_wait_dma_finish(struct meson_nfc *nfc)
328 meson_nfc_drain_cmd(nfc);
330 return meson_nfc_wait_cmd_finish(nfc, DMA_BUSY_TIMEOUT);
392 static int meson_nfc_queue_rb(struct meson_nfc *nfc, int timeout_ms)
397 meson_nfc_cmd_idle(nfc, nfc->timing.twb);
398 meson_nfc_drain_cmd(nfc);
399 meson_nfc_wait_cmd_finish(nfc, CMD_FIFO_EMPTY_TIMEOUT);
401 cfg = readl(nfc->reg_base + NFC_REG_CFG);
403 writel(cfg, nfc->reg_base + NFC_REG_CFG);
405 reinit_completion(&nfc->completion);
409 | nfc->param.chip_select | nfc->timing.tbers_max;
410 writel(cmd, nfc->reg_base + NFC_REG_CMD);
412 ret = wait_for_completion_timeout(&nfc->completion,
479 struct meson_nfc *nfc = nand_get_controller_data(nand);
483 nfc->daddr = dma_map_single(nfc->dev, databuf, datalen, dir);
484 ret = dma_mapping_error(nfc->dev, nfc->daddr);
486 dev_err(nfc->dev, "DMA mapping error\n");
489 cmd = GENCMDDADDRL(NFC_CMD_ADL, nfc->daddr);
490 writel(cmd, nfc->reg_base + NFC_REG_CMD);
492 cmd = GENCMDDADDRH(NFC_CMD_ADH, nfc->daddr);
493 writel(cmd, nfc->reg_base + NFC_REG_CMD);
496 nfc->iaddr = dma_map_single(nfc->dev, infobuf, infolen, dir);
497 ret = dma_mapping_error(nfc->dev, nfc->iaddr);
499 dev_err(nfc->dev, "DMA mapping error\n");
500 dma_unmap_single(nfc->dev,
501 nfc->daddr, datalen, dir);
504 nfc->info_bytes = infolen;
505 cmd = GENCMDIADDRL(NFC_CMD_AIL, nfc->iaddr);
506 writel(cmd, nfc->reg_base + NFC_REG_CMD);
508 cmd = GENCMDIADDRH(NFC_CMD_AIH, nfc->iaddr);
509 writel(cmd, nfc->reg_base + NFC_REG_CMD);
519 struct meson_nfc *nfc = nand_get_controller_data(nand);
521 dma_unmap_single(nfc->dev, nfc->daddr, datalen, dir);
523 dma_unmap_single(nfc->dev, nfc->iaddr, infolen, dir);
524 nfc->info_bytes = 0;
530 struct meson_nfc *nfc = nand_get_controller_data(nand);
545 writel(cmd, nfc->reg_base + NFC_REG_CMD);
547 meson_nfc_drain_cmd(nfc);
548 meson_nfc_wait_cmd_finish(nfc, 1000);
559 struct meson_nfc *nfc = nand_get_controller_data(nand);
569 writel(cmd, nfc->reg_base + NFC_REG_CMD);
571 meson_nfc_drain_cmd(nfc);
572 meson_nfc_wait_cmd_finish(nfc, 1000);
584 struct meson_nfc *nfc = nand_get_controller_data(nand);
585 u32 *addrs = nfc->cmdfifo.rw.addrs;
586 u32 cs = nfc->param.chip_select;
593 nfc->cmdfifo.rw.cmd0 = cs | NFC_CMD_CLE | cmd0;
617 writel_relaxed(nfc->cmdfifo.cmd[i],
618 nfc->reg_base + NFC_REG_CMD);
621 nfc->cmdfifo.rw.cmd1 = cs | NFC_CMD_CLE | NAND_CMD_READSTART;
622 writel(nfc->cmdfifo.rw.cmd1, nfc->reg_base + NFC_REG_CMD);
623 meson_nfc_queue_rb(nfc, PSEC_TO_MSEC(sdr->tR_max));
625 meson_nfc_cmd_idle(nfc, nfc->timing.tadl);
638 struct meson_nfc *nfc = nand_get_controller_data(nand);
659 meson_nfc_cmd_seed(nfc, page);
667 cmd = nfc->param.chip_select | NFC_CMD_CLE | NAND_CMD_PAGEPROG;
668 writel(cmd, nfc->reg_base + NFC_REG_CMD);
669 meson_nfc_queue_rb(nfc, PSEC_TO_MSEC(sdr->tPROG_max));
700 static void meson_nfc_check_ecc_pages_valid(struct meson_nfc *nfc,
712 /* info is updated by nfc dma engine*/
714 dma_sync_single_for_cpu(nfc->dev, nfc->iaddr, nfc->info_bytes,
724 struct meson_nfc *nfc = nand_get_controller_data(nand);
745 meson_nfc_cmd_seed(nfc, page);
753 ret = meson_nfc_wait_dma_finish(nfc);
754 meson_nfc_check_ecc_pages_valid(nfc, nand, raw);
906 struct meson_nfc *nfc = nand_get_controller_data(nand);
923 cmd = nfc->param.chip_select | NFC_CMD_CLE;
925 writel(cmd, nfc->reg_base + NFC_REG_CMD);
926 meson_nfc_cmd_idle(nfc, delay_idle);
931 cmd = nfc->param.chip_select | NFC_CMD_ALE;
933 writel(cmd, nfc->reg_base + NFC_REG_CMD);
935 meson_nfc_cmd_idle(nfc, delay_idle);
955 meson_nfc_queue_rb(nfc, instr->ctx.waitrdy.timeout_ms);
957 meson_nfc_cmd_idle(nfc, delay_idle);
961 meson_nfc_wait_cmd_finish(nfc, 1000);
998 static int meson_nfc_clk_init(struct meson_nfc *nfc)
1003 nfc->core_clk = devm_clk_get(nfc->dev, "core");
1004 if (IS_ERR(nfc->core_clk)) {
1005 dev_err(nfc->dev, "failed to get core clock\n");
1006 return PTR_ERR(nfc->core_clk);
1009 nfc->device_clk = devm_clk_get(nfc->dev, "device");
1010 if (IS_ERR(nfc->device_clk)) {
1011 dev_err(nfc->dev, "failed to get device clock\n");
1012 return PTR_ERR(nfc->device_clk);
1015 nfc->phase_tx = devm_clk_get(nfc->dev, "tx");
1016 if (IS_ERR(nfc->phase_tx)) {
1017 dev_err(nfc->dev, "failed to get TX clk\n");
1018 return PTR_ERR(nfc->phase_tx);
1021 nfc->phase_rx = devm_clk_get(nfc->dev, "rx");
1022 if (IS_ERR(nfc->phase_rx)) {
1023 dev_err(nfc->dev, "failed to get RX clk\n");
1024 return PTR_ERR(nfc->phase_rx);
1028 regmap_update_bits(nfc->reg_clk,
1031 ret = clk_prepare_enable(nfc->core_clk);
1033 dev_err(nfc->dev, "failed to enable core clock\n");
1037 ret = clk_prepare_enable(nfc->device_clk);
1039 dev_err(nfc->dev, "failed to enable device clock\n");
1043 ret = clk_prepare_enable(nfc->phase_tx);
1045 dev_err(nfc->dev, "failed to enable TX clock\n");
1049 ret = clk_prepare_enable(nfc->phase_rx);
1051 dev_err(nfc->dev, "failed to enable RX clock\n");
1055 ret = clk_set_rate(nfc->device_clk, 24000000);
1062 clk_disable_unprepare(nfc->phase_rx);
1064 clk_disable_unprepare(nfc->phase_tx);
1066 clk_disable_unprepare(nfc->device_clk);
1068 clk_disable_unprepare(nfc->core_clk);
1072 static void meson_nfc_disable_clk(struct meson_nfc *nfc)
1074 clk_disable_unprepare(nfc->phase_rx);
1075 clk_disable_unprepare(nfc->phase_tx);
1076 clk_disable_unprepare(nfc->device_clk);
1077 clk_disable_unprepare(nfc->core_clk);
1180 struct meson_nfc *nfc = nand_get_controller_data(nand);
1186 mtd->name = devm_kasprintf(nfc->dev, GFP_KERNEL,
1188 dev_name(nfc->dev),
1199 ret = nand_ecc_choose_conf(nand, nfc->data->ecc_caps,
1202 dev_err(nfc->dev, "failed to ECC init\n");
1224 dev_err(nfc->dev, "16bits bus width not supported");
1243 struct meson_nfc *nfc, struct device_node *np)
1272 if (test_and_set_bit(tmp, &nfc->assigned_cs)) {
1279 nand->controller = &nfc->controller;
1282 nand_set_controller_data(nand, nfc);
1300 list_add_tail(&meson_chip->node, &nfc->chips);
1305 static int meson_nfc_nand_chip_cleanup(struct meson_nfc *nfc)
1311 while (!list_empty(&nfc->chips)) {
1312 meson_chip = list_first_entry(&nfc->chips,
1327 struct meson_nfc *nfc)
1334 ret = meson_nfc_nand_chip_init(dev, nfc, nand_np);
1336 meson_nfc_nand_chip_cleanup(nfc);
1347 struct meson_nfc *nfc = id;
1350 cfg = readl(nfc->reg_base + NFC_REG_CFG);
1355 writel(cfg, nfc->reg_base + NFC_REG_CFG);
1357 complete(&nfc->completion);
1371 .compatible = "amlogic,meson-gxl-nfc",
1374 .compatible = "amlogic,meson-axg-nfc",
1384 struct meson_nfc *nfc;
1388 nfc = devm_kzalloc(dev, sizeof(*nfc), GFP_KERNEL);
1389 if (!nfc)
1392 nfc->data = of_device_get_match_data(&pdev->dev);
1393 if (!nfc->data)
1396 nand_controller_init(&nfc->controller);
1397 INIT_LIST_HEAD(&nfc->chips);
1398 init_completion(&nfc->completion);
1400 nfc->dev = dev;
1403 nfc->reg_base = devm_ioremap_resource(dev, res);
1404 if (IS_ERR(nfc->reg_base))
1405 return PTR_ERR(nfc->reg_base);
1407 nfc->reg_clk =
1410 if (IS_ERR(nfc->reg_clk)) {
1412 return PTR_ERR(nfc->reg_clk);
1419 ret = meson_nfc_clk_init(nfc);
1425 writel(0, nfc->reg_base + NFC_REG_CFG);
1426 ret = devm_request_irq(dev, irq, meson_nfc_irq, 0, dev_name(dev), nfc);
1439 platform_set_drvdata(pdev, nfc);
1441 ret = meson_nfc_nand_chips_init(dev, nfc);
1449 meson_nfc_disable_clk(nfc);
1455 struct meson_nfc *nfc = platform_get_drvdata(pdev);
1458 ret = meson_nfc_nand_chip_cleanup(nfc);
1462 meson_nfc_disable_clk(nfc);