Lines Matching defs:host
238 static void lpc32xx_nand_setup(struct lpc32xx_nand_host *host)
243 writel(SLCCTRL_SW_RESET, SLC_CTRL(host->io_base));
247 writel(0, SLC_CFG(host->io_base));
248 writel(0, SLC_IEN(host->io_base));
250 SLC_ICR(host->io_base));
253 clkrate = clk_get_rate(host->clk);
258 tmp = SLCTAC_WDR(host->ncfg->wdr_clks) |
259 SLCTAC_WWIDTH(clkrate, host->ncfg->wwidth) |
260 SLCTAC_WHOLD(clkrate, host->ncfg->whold) |
261 SLCTAC_WSETUP(clkrate, host->ncfg->wsetup) |
262 SLCTAC_RDR(host->ncfg->rdr_clks) |
263 SLCTAC_RWIDTH(clkrate, host->ncfg->rwidth) |
264 SLCTAC_RHOLD(clkrate, host->ncfg->rhold) |
265 SLCTAC_RSETUP(clkrate, host->ncfg->rsetup);
266 writel(tmp, SLC_TAC(host->io_base));
276 struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
279 tmp = readl(SLC_CFG(host->io_base));
284 writel(tmp, SLC_CFG(host->io_base));
288 writel(cmd, SLC_CMD(host->io_base));
290 writel(cmd, SLC_ADDR(host->io_base));
299 struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
302 if ((readl(SLC_STAT(host->io_base)) & SLCSTAT_NAND_READY) != 0)
311 static void lpc32xx_wp_enable(struct lpc32xx_nand_host *host)
313 if (gpio_is_valid(host->ncfg->wp_gpio))
314 gpio_set_value(host->ncfg->wp_gpio, 0);
320 static void lpc32xx_wp_disable(struct lpc32xx_nand_host *host)
322 if (gpio_is_valid(host->ncfg->wp_gpio))
323 gpio_set_value(host->ncfg->wp_gpio, 1);
353 struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
355 return (uint8_t)readl(SLC_DATA(host->io_base));
363 struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
367 *buf++ = (uint8_t)readl(SLC_DATA(host->io_base));
376 struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
380 writel((uint32_t)*buf++, SLC_DATA(host->io_base));
431 struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
436 host->dma_slave_config.direction = dir;
437 host->dma_slave_config.src_addr = dma;
438 host->dma_slave_config.dst_addr = dma;
439 host->dma_slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
440 host->dma_slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
441 host->dma_slave_config.src_maxburst = 4;
442 host->dma_slave_config.dst_maxburst = 4;
444 host->dma_slave_config.device_fc = false;
445 if (dmaengine_slave_config(host->dma_chan, &host->dma_slave_config)) {
450 sg_init_one(&host->sgl, mem, len);
452 res = dma_map_sg(host->dma_chan->device->dev, &host->sgl, 1,
458 desc = dmaengine_prep_slave_sg(host->dma_chan, &host->sgl, 1, dir,
465 init_completion(&host->comp);
467 desc->callback_param = &host->comp;
470 dma_async_issue_pending(host->dma_chan);
472 wait_for_completion_timeout(&host->comp, msecs_to_jiffies(1000));
474 dma_unmap_sg(host->dma_chan->device->dev, &host->sgl, 1,
479 dma_unmap_sg(host->dma_chan->device->dev, &host->sgl, 1,
491 struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
504 dma_buf = host->data_buf;
507 memcpy(host->data_buf, buf, mtd->writesize);
511 writel(readl(SLC_CFG(host->io_base)) |
513 SLCCFG_DMA_BURST, SLC_CFG(host->io_base));
515 writel((readl(SLC_CFG(host->io_base)) |
518 SLC_CFG(host->io_base));
522 writel(SLCCTRL_ECC_CLEAR, SLC_CTRL(host->io_base));
525 writel(mtd->writesize, SLC_TC(host->io_base));
528 writel(readl(SLC_CTRL(host->io_base)) | SLCCTRL_DMA_START,
529 SLC_CTRL(host->io_base));
533 res = lpc32xx_xmit_dma(mtd, SLC_DMA_DATA(host->io_base_dma),
544 res = lpc32xx_xmit_dma(mtd, SLC_ECC(host->io_base_dma),
545 &host->ecc_buf[i], 4, DMA_DEV_TO_MEM);
557 if (readl(SLC_STAT(host->io_base)) & SLCSTAT_DMA_FIFO) {
560 while ((readl(SLC_STAT(host->io_base)) & SLCSTAT_DMA_FIFO) &&
572 host->ecc_buf[chip->ecc.steps - 1] =
573 readl(SLC_ECC(host->io_base));
576 dmaengine_terminate_all(host->dma_chan);
578 if (readl(SLC_STAT(host->io_base)) & SLCSTAT_DMA_FIFO ||
579 readl(SLC_TC(host->io_base))) {
586 writel(readl(SLC_CTRL(host->io_base)) & ~SLCCTRL_DMA_START,
587 SLC_CTRL(host->io_base));
588 writel(readl(SLC_CFG(host->io_base)) &
590 SLCCFG_DMA_BURST), SLC_CFG(host->io_base));
593 memcpy(buf, host->data_buf, mtd->writesize);
606 struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
621 lpc32xx_slc_ecc_copy(tmpecc, (uint32_t *) host->ecc_buf, chip->ecc.steps);
674 struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
695 lpc32xx_slc_ecc_copy(pb, (uint32_t *)host->ecc_buf, chip->ecc.steps);
721 static int lpc32xx_nand_dma_setup(struct lpc32xx_nand_host *host)
723 struct mtd_info *mtd = nand_to_mtd(&host->nand_chip);
726 if (!host->pdata || !host->pdata->dma_filter) {
733 host->dma_chan = dma_request_channel(mask, host->pdata->dma_filter,
735 if (!host->dma_chan) {
776 struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
782 host->ecc_buf = (uint32_t *)(host->data_buf + LPC32XX_DMA_DATA_SIZE);
832 struct lpc32xx_nand_host *host;
839 host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL);
840 if (!host)
844 host->io_base = devm_ioremap_resource(&pdev->dev, rc);
845 if (IS_ERR(host->io_base))
846 return PTR_ERR(host->io_base);
848 host->io_base_dma = rc->start;
850 host->ncfg = lpc32xx_parse_dt(&pdev->dev);
851 if (!host->ncfg) {
856 if (host->ncfg->wp_gpio == -EPROBE_DEFER)
858 if (gpio_is_valid(host->ncfg->wp_gpio) && devm_gpio_request(&pdev->dev,
859 host->ncfg->wp_gpio, "NAND WP")) {
863 lpc32xx_wp_disable(host);
865 host->pdata = dev_get_platdata(&pdev->dev);
867 chip = &host->nand_chip;
869 nand_set_controller_data(chip, host);
875 host->clk = devm_clk_get(&pdev->dev, NULL);
876 if (IS_ERR(host->clk)) {
881 res = clk_prepare_enable(host->clk);
886 chip->legacy.IO_ADDR_R = SLC_DATA(host->io_base);
887 chip->legacy.IO_ADDR_W = SLC_DATA(host->io_base);
893 lpc32xx_nand_setup(host);
895 platform_set_drvdata(pdev, host);
906 host->dma_buf_len = LPC32XX_DMA_DATA_SIZE + LPC32XX_ECC_SAVE_SIZE;
907 host->data_buf = devm_kzalloc(&pdev->dev, host->dma_buf_len,
909 if (host->data_buf == NULL) {
914 res = lpc32xx_nand_dma_setup(host);
927 res = mtd_device_register(mtd, host->ncfg->parts,
928 host->ncfg->num_parts);
937 dma_release_channel(host->dma_chan);
939 clk_disable_unprepare(host->clk);
941 lpc32xx_wp_enable(host);
952 struct lpc32xx_nand_host *host = platform_get_drvdata(pdev);
953 struct nand_chip *chip = &host->nand_chip;
959 dma_release_channel(host->dma_chan);
962 tmp = readl(SLC_CTRL(host->io_base));
964 writel(tmp, SLC_CTRL(host->io_base));
966 clk_disable_unprepare(host->clk);
967 lpc32xx_wp_enable(host);
975 struct lpc32xx_nand_host *host = platform_get_drvdata(pdev);
979 ret = clk_prepare_enable(host->clk);
984 lpc32xx_nand_setup(host);
987 lpc32xx_wp_disable(host);
995 struct lpc32xx_nand_host *host = platform_get_drvdata(pdev);
998 tmp = readl(SLC_CTRL(host->io_base));
1000 writel(tmp, SLC_CTRL(host->io_base));
1003 lpc32xx_wp_enable(host);
1006 clk_disable_unprepare(host->clk);