Lines Matching defs:host
232 static void lpc32xx_nand_setup(struct lpc32xx_nand_host *host)
237 writel(MLCCMD_RESET, MLC_CMD(host->io_base));
241 clkrate = clk_get_rate(host->clk);
247 writew(MLCLOCKPR_MAGIC, MLC_LOCK_PR(host->io_base));
251 writel(tmp, MLC_ICR(host->io_base));
255 writew(MLCLOCKPR_MAGIC, MLC_LOCK_PR(host->io_base));
259 tmp |= MLCTIMEREG_TCEA_DELAY(clkrate / host->ncfg->tcea_delay + 1);
260 tmp |= MLCTIMEREG_BUSY_DELAY(clkrate / host->ncfg->busy_delay + 1);
261 tmp |= MLCTIMEREG_NAND_TA(clkrate / host->ncfg->nand_ta + 1);
262 tmp |= MLCTIMEREG_RD_HIGH(clkrate / host->ncfg->rd_high + 1);
263 tmp |= MLCTIMEREG_RD_LOW(clkrate / host->ncfg->rd_low);
264 tmp |= MLCTIMEREG_WR_HIGH(clkrate / host->ncfg->wr_high + 1);
265 tmp |= MLCTIMEREG_WR_LOW(clkrate / host->ncfg->wr_low);
266 writel(tmp, MLC_TIME_REG(host->io_base));
270 MLC_IRQ_MR(host->io_base));
273 writel(MLCCEH_NORMAL, MLC_CEH(host->io_base));
282 struct lpc32xx_nand_host *host = nand_get_controller_data(nand_chip);
286 writel(cmd, MLC_CMD(host->io_base));
288 writel(cmd, MLC_ADDR(host->io_base));
297 struct lpc32xx_nand_host *host = nand_get_controller_data(nand_chip);
299 if ((readb(MLC_ISR(host->io_base)) &
307 static irqreturn_t lpc3xxx_nand_irq(int irq, struct lpc32xx_nand_host *host)
312 sr = readb(MLC_IRQ_SR(host->io_base));
314 complete(&host->comp_nand);
316 complete(&host->comp_controller);
324 struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
326 if (readb(MLC_ISR(host->io_base)) & MLCISR_NAND_READY)
329 wait_for_completion(&host->comp_nand);
331 while (!(readb(MLC_ISR(host->io_base)) & MLCISR_NAND_READY)) {
344 struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
346 if (readb(MLC_ISR(host->io_base)) & MLCISR_CONTROLLER_READY)
349 wait_for_completion(&host->comp_controller);
351 while (!(readb(MLC_ISR(host->io_base)) &
372 static void lpc32xx_wp_enable(struct lpc32xx_nand_host *host)
374 if (gpio_is_valid(host->ncfg->wp_gpio))
375 gpio_set_value(host->ncfg->wp_gpio, 0);
381 static void lpc32xx_wp_disable(struct lpc32xx_nand_host *host)
383 if (gpio_is_valid(host->ncfg->wp_gpio))
384 gpio_set_value(host->ncfg->wp_gpio, 1);
396 struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
401 sg_init_one(&host->sgl, mem, len);
403 res = dma_map_sg(host->dma_chan->device->dev, &host->sgl, 1,
409 desc = dmaengine_prep_slave_sg(host->dma_chan, &host->sgl, 1, dir,
416 init_completion(&host->comp_dma);
418 desc->callback_param = &host->comp_dma;
421 dma_async_issue_pending(host->dma_chan);
423 wait_for_completion_timeout(&host->comp_dma, msecs_to_jiffies(1000));
425 dma_unmap_sg(host->dma_chan->device->dev, &host->sgl, 1,
429 dma_unmap_sg(host->dma_chan->device->dev, &host->sgl, 1,
438 struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
450 dma_buf = host->dma_buf;
458 for (i = 0; i < host->mlcsubpages; i++) {
460 writeb(0x00, MLC_ECC_AUTO_DEC_REG(host->io_base));
466 mlc_isr = readl(MLC_ISR(host->io_base));
483 readl(MLC_BUFF(host->io_base));
489 readl(MLC_BUFF(host->io_base));
505 struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
512 dma_buf = host->dma_buf;
518 for (i = 0; i < host->mlcsubpages; i++) {
520 writeb(0x00, MLC_ECC_ENC_REG(host->io_base));
531 MLC_BUFF(host->io_base));
535 writel(*((uint32_t *)(oobbuf)), MLC_BUFF(host->io_base));
537 writew(*((uint16_t *)(oobbuf)), MLC_BUFF(host->io_base));
541 writeb(0x00, MLC_ECC_AUTO_ENC_REG(host->io_base));
552 struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
555 lpc32xx_read_page(chip, host->dummy_buf, 1, page);
572 static int lpc32xx_dma_setup(struct lpc32xx_nand_host *host)
574 struct mtd_info *mtd = nand_to_mtd(&host->nand_chip);
577 if (!host->pdata || !host->pdata->dma_filter) {
584 host->dma_chan = dma_request_channel(mask, host->pdata->dma_filter,
586 if (!host->dma_chan) {
596 host->dma_slave_config.direction = DMA_DEV_TO_MEM;
597 host->dma_slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
598 host->dma_slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
599 host->dma_slave_config.src_maxburst = 128;
600 host->dma_slave_config.dst_maxburst = 128;
602 host->dma_slave_config.device_fc = false;
603 host->dma_slave_config.src_addr = MLC_BUFF(host->io_base_phy);
604 host->dma_slave_config.dst_addr = MLC_BUFF(host->io_base_phy);
605 if (dmaengine_slave_config(host->dma_chan, &host->dma_slave_config)) {
612 dma_release_channel(host->dma_chan);
648 struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
649 struct device *dev = &host->pdev->dev;
654 host->dma_buf = devm_kzalloc(dev, mtd->writesize, GFP_KERNEL);
655 if (!host->dma_buf)
658 host->dummy_buf = devm_kzalloc(dev, mtd->writesize, GFP_KERNEL);
659 if (!host->dummy_buf)
674 host->mlcsubpages = mtd->writesize / 512;
688 struct lpc32xx_nand_host *host;
695 host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL);
696 if (!host)
699 host->pdev = pdev;
702 host->io_base = devm_ioremap_resource(&pdev->dev, rc);
703 if (IS_ERR(host->io_base))
704 return PTR_ERR(host->io_base);
706 host->io_base_phy = rc->start;
708 nand_chip = &host->nand_chip;
711 host->ncfg = lpc32xx_parse_dt(&pdev->dev);
712 if (!host->ncfg) {
717 if (host->ncfg->wp_gpio == -EPROBE_DEFER)
719 if (gpio_is_valid(host->ncfg->wp_gpio) &&
720 gpio_request(host->ncfg->wp_gpio, "NAND WP")) {
724 lpc32xx_wp_disable(host);
726 host->pdata = dev_get_platdata(&pdev->dev);
729 nand_set_controller_data(nand_chip, host);
734 host->clk = clk_get(&pdev->dev, NULL);
735 if (IS_ERR(host->clk)) {
740 res = clk_prepare_enable(host->clk);
747 nand_chip->legacy.IO_ADDR_R = MLC_DATA(host->io_base);
748 nand_chip->legacy.IO_ADDR_W = MLC_DATA(host->io_base);
751 lpc32xx_nand_setup(host);
753 platform_set_drvdata(pdev, host);
764 res = lpc32xx_dma_setup(host);
772 readb(MLC_IRQ_SR(host->io_base));
774 init_completion(&host->comp_nand);
775 init_completion(&host->comp_controller);
777 host->irq = platform_get_irq(pdev, 0);
778 if (host->irq < 0) {
783 if (request_irq(host->irq, (irq_handler_t)&lpc3xxx_nand_irq,
784 IRQF_TRIGGER_HIGH, DRV_NAME, host)) {
801 res = mtd_device_register(mtd, host->ncfg->parts,
802 host->ncfg->num_parts);
811 free_irq(host->irq, host);
814 dma_release_channel(host->dma_chan);
816 clk_disable_unprepare(host->clk);
818 clk_put(host->clk);
820 lpc32xx_wp_enable(host);
821 gpio_free(host->ncfg->wp_gpio);
831 struct lpc32xx_nand_host *host = platform_get_drvdata(pdev);
832 struct nand_chip *chip = &host->nand_chip;
839 free_irq(host->irq, host);
841 dma_release_channel(host->dma_chan);
843 clk_disable_unprepare(host->clk);
844 clk_put(host->clk);
846 lpc32xx_wp_enable(host);
847 gpio_free(host->ncfg->wp_gpio);
855 struct lpc32xx_nand_host *host = platform_get_drvdata(pdev);
859 ret = clk_prepare_enable(host->clk);
864 lpc32xx_nand_setup(host);
867 lpc32xx_wp_disable(host);
874 struct lpc32xx_nand_host *host = platform_get_drvdata(pdev);
877 lpc32xx_wp_enable(host);
880 clk_disable_unprepare(host->clk);