Lines Matching refs:info
70 static inline unsigned int davinci_nand_readl(struct davinci_nand_info *info,
73 return __raw_readl(info->base + offset);
76 static inline void davinci_nand_writel(struct davinci_nand_info *info,
79 __raw_writel(value, info->base + offset);
90 struct davinci_nand_info *info = to_davinci_nand(mtd);
92 return davinci_nand_readl(info, NANDF1ECC_OFFSET
93 + 4 * info->core_chipsel);
98 struct davinci_nand_info *info;
102 info = to_davinci_nand(nand_to_mtd(chip));
110 nandcfr = davinci_nand_readl(info, NANDFCR_OFFSET);
111 nandcfr |= BIT(8 + info->core_chipsel);
112 davinci_nand_writel(info, NANDFCR_OFFSET, nandcfr);
182 struct davinci_nand_info *info = to_davinci_nand(nand_to_mtd(chip));
187 davinci_nand_readl(info, NAND_4BIT_ECC1_OFFSET);
192 val = davinci_nand_readl(info, NANDFCR_OFFSET);
194 val |= (info->core_chipsel << 4) | BIT(12);
195 davinci_nand_writel(info, NANDFCR_OFFSET, val);
197 info->is_readmode = (mode == NAND_ECC_READ);
204 nand_davinci_readecc_4bit(struct davinci_nand_info *info, u32 code[4])
208 code[0] = davinci_nand_readl(info, NAND_4BIT_ECC1_OFFSET) & mask;
209 code[1] = davinci_nand_readl(info, NAND_4BIT_ECC2_OFFSET) & mask;
210 code[2] = davinci_nand_readl(info, NAND_4BIT_ECC3_OFFSET) & mask;
211 code[3] = davinci_nand_readl(info, NAND_4BIT_ECC4_OFFSET) & mask;
218 struct davinci_nand_info *info = to_davinci_nand(nand_to_mtd(chip));
227 if (info->is_readmode) {
228 davinci_nand_readl(info, NAND_4BIT_ECC1_OFFSET);
237 nand_davinci_readecc_4bit(info, raw_ecc);
256 struct davinci_nand_info *info = to_davinci_nand(nand_to_mtd(chip));
282 davinci_nand_writel(info, NAND_4BIT_ECC_LOAD_OFFSET, ecc10[i]);
287 davinci_nand_readl(info, NANDFSR_OFFSET);
288 nand_davinci_readecc_4bit(info, syndrome);
296 davinci_nand_readl(info, NAND_ERR_ADD1_OFFSET);
302 davinci_nand_writel(info, NANDFCR_OFFSET,
303 davinci_nand_readl(info, NANDFCR_OFFSET) | BIT(13));
316 ecc_state = (davinci_nand_readl(info,
322 u32 fsr = davinci_nand_readl(info, NANDFSR_OFFSET);
326 davinci_nand_readl(info, NAND_ERR_ERRVAL1_OFFSET);
329 davinci_nand_readl(info, NAND_ERR_ERRVAL1_OFFSET);
347 error_address = davinci_nand_readl(info,
349 error_value = davinci_nand_readl(info,
352 error_address = davinci_nand_readl(info,
354 error_value = davinci_nand_readl(info,
377 * @chip: nand chip info structure
577 struct davinci_nand_info *info = to_davinci_nand(mtd);
578 struct davinci_nand_pdata *pdata = nand_davinci_get_pdata(info->pdev);
585 info->chip.ecc.engine_type = pdata->engine_type;
586 info->chip.ecc.placement = pdata->ecc_placement;
588 switch (info->chip.ecc.engine_type) {
600 info->chip.ecc.algo = NAND_ECC_ALGO_HAMMING;
607 dev_dbg(&info->pdev->dev, "too small\n");
627 info->chip.ecc.calculate = nand_davinci_calculate_4bit;
628 info->chip.ecc.correct = nand_davinci_correct_4bit;
629 info->chip.ecc.hwctl = nand_davinci_hwctl_4bit;
630 info->chip.ecc.bytes = 10;
631 info->chip.ecc.options = NAND_ECC_GENERIC_ERASED_CHECK;
632 info->chip.ecc.algo = NAND_ECC_ALGO_BCH;
650 info->chip.ecc.read_page = nand_davinci_read_page_hwecc_oob_first;
656 info->chip.ecc.calculate = nand_davinci_calculate_1bit;
657 info->chip.ecc.correct = nand_davinci_correct_1bit;
658 info->chip.ecc.hwctl = nand_davinci_hwctl_1bit;
659 info->chip.ecc.bytes = 3;
660 info->chip.ecc.algo = NAND_ECC_ALGO_HAMMING;
662 info->chip.ecc.size = 512;
663 info->chip.ecc.strength = pdata->ecc_bits;
672 static void nand_davinci_data_in(struct davinci_nand_info *info, void *buf,
678 ioread8_rep(info->current_cs, buf, len);
680 ioread16_rep(info->current_cs, buf, len >> 1);
682 ioread32_rep(info->current_cs, buf, len >> 2);
685 static void nand_davinci_data_out(struct davinci_nand_info *info,
692 iowrite8_rep(info->current_cs, buf, len);
694 iowrite16_rep(info->current_cs, buf, len >> 1);
696 iowrite32_rep(info->current_cs, buf, len >> 2);
699 static int davinci_nand_exec_instr(struct davinci_nand_info *info,
709 info->current_cs + info->mask_cle);
715 info->current_cs + info->mask_ale);
720 nand_davinci_data_in(info, instr->ctx.data.buf.in,
726 nand_davinci_data_out(info, instr->ctx.data.buf.out,
733 ret = readl_relaxed_poll_timeout(info->base + NANDFSR_OFFSET,
752 struct davinci_nand_info *info = to_davinci_nand(nand_to_mtd(chip));
758 info->current_cs = info->vaddr + (op->cs * info->mask_chipsel);
763 ret = davinci_nand_exec_instr(info, &op->instrs[i]);
779 struct davinci_nand_info *info;
800 info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
801 if (!info)
804 platform_set_drvdata(pdev, info);
829 info->pdev = pdev;
830 info->base = base;
831 info->vaddr = vaddr;
833 mtd = nand_to_mtd(&info->chip);
835 nand_set_flash_node(&info->chip, pdev->dev.of_node);
838 info->chip.bbt_options = pdata->bbt_options;
840 info->chip.options = pdata->options;
841 info->chip.bbt_td = pdata->bbt_td;
842 info->chip.bbt_md = pdata->bbt_md;
843 info->timing = pdata->timing;
845 info->current_cs = info->vaddr;
846 info->core_chipsel = pdata->core_chipsel;
847 info->mask_chipsel = pdata->mask_chipsel;
850 info->mask_ale = pdata->mask_ale ? : MASK_ALE;
851 info->mask_cle = pdata->mask_cle ? : MASK_CLE;
856 val = davinci_nand_readl(info, NANDFCR_OFFSET);
857 val |= BIT(info->core_chipsel);
858 davinci_nand_writel(info, NANDFCR_OFFSET, val);
863 nand_controller_init(&info->controller);
864 info->controller.ops = &davinci_nand_controller_ops;
865 info->chip.controller = &info->controller;
866 ret = nand_scan(&info->chip, pdata->mask_chipsel ? 2 : 1);
879 val = davinci_nand_readl(info, NRCSR_OFFSET);
886 nand_cleanup(&info->chip);
893 struct davinci_nand_info *info = platform_get_drvdata(pdev);
894 struct nand_chip *chip = &info->chip;
898 if (info->chip.ecc.placement == NAND_ECC_PLACEMENT_INTERLEAVED)