Lines Matching defs:data
42 * Writing data to this register will initiate a new transaction
100 * Configures data transfer parameters.
110 * Configures data transfer parameters.
113 /* Size of last data sector. */
115 /* Size of not-last data sector. */
140 /* Transferred data block size for the slave DMA module. */
143 /* Thread number associated with transferred data block
167 /* Slave and Master DMA data width. */
286 /* Generic data transfer sequence type. */
297 /* Transfer direction field of generic command data sequence. */
299 /* Read transfer direction of generic command data sequence. */
301 /* Write transfer direction of generic command data sequence. */
304 /* ECC enabled flag of generic command data sequence - ECC enabled. */
306 /* Generic command data sequence - sector size. */
308 /* Generic command data sequence - sector count. */
310 /* Generic command data sequence - last sector size. */
405 /* System/host memory address required for data DMA commands. */
419 /* Control data pointer. */
433 /* Cadence NAND flash controller capabilities get from driver data. */
445 /* Slave and Master DMA data width in bytes (4 or 8). */
495 * associated with data read capture.
683 /* Functions enables/disables hardware detection of erased data */
861 /* Wait for data on slave DMA interface. */
1087 "Driver needs at least 4 bytes of BCH meta data\n");
1202 /* Prepare size of data to transfer. */
1442 /* Set oob data to 0xFF. */
1475 /* Transfer the data to the oob area. */
1627 * If data buffer can be accessed by DMA and data_control feature
1628 * is supported then transfer data and oob directly.
1688 /* Reads OOB data from the device. */
1804 static void cadence_nand_slave_dma_transfer_finished(void *data)
1806 struct completion *finished = data;
1879 /* Wait until slave DMA interface is ready to data transfer. */
1887 /* read alingment data */
1890 /* read rest data from slave DMA interface if any */
1893 /* copy rest of data */
1933 /* Wait until slave DMA interface is ready to data transfer. */
1943 /* copy rest of data */
1946 /* write all expected by nand controller data */
2139 if (instr->ctx.data.force_8bit) {
2143 "cannot change byte access generic data cmd failed\n");
2152 dev_err(cdns_ctrl->dev, "send generic data cmd failed\n");
2157 void *buf = instr->ctx.data.buf.in + offset;
2161 const void *buf = instr->ctx.data.buf.out + offset;
2167 dev_err(cdns_ctrl->dev, "data transfer failed for generic command\n");
2171 if (instr->ctx.data.force_8bit) {
2175 "cannot change byte access generic data cmd failed\n");
2285 /* Calculate max data valid window. */
2296 /* Calculate data valid window. */
2348 * for tRP and tRH timings. If it is NOT possible to sample data
2366 * Check if data valid window and sampling point can be found
2382 * to be able to sample data the tRP need to be widen.
2405 * Check if data valid window and sampling point can be found
2431 * There is no valid window to be able to sample data.
2502 * The following is related to the we edge of the random data input
2555 * of data and being odd number.
2943 .data = &cadence_nand_default
2961 ofdev->id_entry = of_id->data;
2962 devdata = of_id->data;