Lines Matching defs:ecc
761 /* v7.2 has different ecc level shift in the acc register */
1228 .ecc = brcmnand_hamming_ooblayout_ecc,
1244 oobregion->offset = ((section + 1) * sas) - chip->ecc.bytes;
1245 oobregion->length = chip->ecc.bytes;
1262 if (sas <= chip->ecc.bytes)
1266 oobregion->length = sas - chip->ecc.bytes;
1284 if (section > 1 || sas - chip->ecc.bytes < 6 ||
1285 (section && sas - chip->ecc.bytes == 6))
1293 oobregion->length = sas - chip->ecc.bytes - 6;
1300 .ecc = brcmnand_bch_ooblayout_ecc,
1305 .ecc = brcmnand_bch_ooblayout_ecc,
1313 struct nand_ecc_ctrl *ecc = &host->chip.ecc;
1322 ecc->bytes = 3 * sectors;
1333 ecc->bytes = DIV_ROUND_UP(ecc_level * 14, 8);
1339 if (ecc->bytes >= sas) {
1342 ecc->bytes, sas);
2158 struct mtd_oob_region ecc;
2169 /* read without ecc for verification */
2170 ret = chip->ecc.read_page_raw(chip, buf, true, page);
2174 for (i = 0; i < chip->ecc.steps; i++) {
2175 ecc_chunk = buf + chip->ecc.size * i;
2177 mtd_ooblayout_ecc(mtd, i, &ecc);
2178 ecc_bytes = chip->oob_poi + ecc.offset;
2180 ret = nand_check_erased_ecc_chunk(ecc_chunk, chip->ecc.size,
2181 ecc_bytes, ecc.length,
2183 chip->ecc.strength);
2552 brcmnand_wr_corr_thresh(host, DIV_ROUND_UP(chip->ecc.strength * 3, 4));
2631 if (chip->ecc.engine_type != NAND_ECC_ENGINE_TYPE_ON_HOST) {
2633 chip->ecc.engine_type);
2637 if (chip->ecc.algo == NAND_ECC_ALGO_UNKNOWN) {
2638 if (chip->ecc.strength == 1 && chip->ecc.size == 512)
2640 chip->ecc.algo = NAND_ECC_ALGO_HAMMING;
2643 chip->ecc.algo = NAND_ECC_ALGO_BCH;
2646 if (chip->ecc.algo == NAND_ECC_ALGO_HAMMING &&
2647 (chip->ecc.strength != 1 || chip->ecc.size != 512)) {
2649 chip->ecc.strength, chip->ecc.size);
2653 if (chip->ecc.engine_type != NAND_ECC_ENGINE_TYPE_NONE &&
2654 (!chip->ecc.size || !chip->ecc.strength)) {
2657 chip->ecc.size = requirements->step_size;
2658 chip->ecc.strength = requirements->strength;
2660 chip->ecc.size, chip->ecc.strength);
2664 switch (chip->ecc.size) {
2666 if (chip->ecc.algo == NAND_ECC_ALGO_HAMMING)
2669 cfg->ecc_level = chip->ecc.strength;
2677 if (chip->ecc.strength & 0x1) {
2683 cfg->ecc_level = chip->ecc.strength >> 1;
2688 chip->ecc.size);
2745 chip->ecc.size = host->hwcfg.sector_size_1k ? 1024 : 512;
2754 chip->ecc.write_oob = brcmnand_write_oob_raw;
2755 chip->ecc.read_oob = brcmnand_read_oob_raw;
2800 chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST;
2801 chip->ecc.read_page = brcmnand_read_page;
2802 chip->ecc.write_page = brcmnand_write_page;
2803 chip->ecc.read_page_raw = brcmnand_read_page_raw;
2804 chip->ecc.write_page_raw = brcmnand_write_page_raw;
2805 chip->ecc.write_oob_raw = brcmnand_write_oob_raw;
2806 chip->ecc.read_oob_raw = brcmnand_read_oob_raw;
2807 chip->ecc.read_oob = brcmnand_read_oob;
2808 chip->ecc.write_oob = brcmnand_write_oob;