Lines Matching defs:sdmmc_base
187 void __iomem *sdmmc_base;
213 u32 reg_tmp = readb(priv->sdmmc_base + SDMMC_BUSMODE);
220 writeb(reg_tmp, priv->sdmmc_base + SDMMC_BUSMODE);
236 tmp_resp = readb(priv->sdmmc_base + SDMMC_RSP);
238 tmp_resp = readb(priv->sdmmc_base + SDMMC_RSP +
250 reg_tmp = readb(priv->sdmmc_base + SDMMC_CTLR);
251 writeb(reg_tmp | CTLR_CMD_START, priv->sdmmc_base + SDMMC_CTLR);
263 writeb(command, priv->sdmmc_base + SDMMC_CMD);
264 writel(arg, priv->sdmmc_base + SDMMC_ARG);
265 writeb(rsptype, priv->sdmmc_base + SDMMC_RSPTYPE);
268 reg_tmp = readb(priv->sdmmc_base + SDMMC_CTLR);
269 writeb(reg_tmp | CTLR_FIFO_RESET, priv->sdmmc_base + SDMMC_CTLR);
275 writeb(0xFF, priv->sdmmc_base + SDMMC_STS0);
276 writeb(0xFF, priv->sdmmc_base + SDMMC_STS1);
277 writeb(0xFF, priv->sdmmc_base + SDMMC_STS2);
278 writeb(0xFF, priv->sdmmc_base + SDMMC_STS3);
281 reg_tmp = readb(priv->sdmmc_base + SDMMC_CTLR);
283 priv->sdmmc_base + SDMMC_CTLR);
290 writel(DMA_ISR_INT_STS, priv->sdmmc_base + SDDMA_ISR);
291 writel(0, priv->sdmmc_base + SDDMA_IER);
341 status = readl(priv->sdmmc_base + SDDMA_CCR) & 0x0F;
381 status0 = readb(priv->sdmmc_base + SDMMC_STS0);
382 status1 = readb(priv->sdmmc_base + SDMMC_STS1);
383 status2 = readb(priv->sdmmc_base + SDMMC_STS2);
386 reg_tmp = readb(priv->sdmmc_base + SDMMC_INTMASK0);
397 writeb(STS0_DEVICE_INS, priv->sdmmc_base + SDMMC_STS0);
455 writeb(status0, priv->sdmmc_base + SDMMC_STS0);
456 writeb(status1, priv->sdmmc_base + SDMMC_STS1);
457 writeb(status2, priv->sdmmc_base + SDMMC_STS2);
470 reg_tmp = readb(priv->sdmmc_base + SDMMC_BUSMODE);
471 writeb(reg_tmp | BM_SOFT_RESET, priv->sdmmc_base + SDMMC_BUSMODE);
474 reg_tmp = readb(priv->sdmmc_base + SDMMC_CTLR);
475 writeb(reg_tmp | CTLR_FIFO_RESET, priv->sdmmc_base + SDMMC_CTLR);
478 writew(BLKL_INT_ENABLE | BLKL_GPI_CD, priv->sdmmc_base + SDMMC_BLKLEN);
481 writeb(0xFF, priv->sdmmc_base + SDMMC_STS0);
482 writeb(0xFF, priv->sdmmc_base + SDMMC_STS1);
485 writeb(INT0_CD_INT_EN | INT0_DI_INT_EN, priv->sdmmc_base +
488 INT1_CMD_RES_TOUT_INT_EN, priv->sdmmc_base + SDMMC_INTMASK1);
491 writew(8191, priv->sdmmc_base + SDMMC_DMATIMEOUT);
494 reg_tmp = readb(priv->sdmmc_base + SDMMC_STS2);
495 writeb(reg_tmp | STS2_DIS_FORCECLK, priv->sdmmc_base + SDMMC_STS2);
507 writel(DMA_GCR_SOFT_RESET, priv->sdmmc_base + SDDMA_GCR);
508 writel(DMA_GCR_DMA_EN, priv->sdmmc_base + SDDMA_GCR);
509 if ((readl(priv->sdmmc_base + SDDMA_GCR) & DMA_GCR_DMA_EN) != 0)
533 writel(DMA_IER_INT_EN, priv->sdmmc_base + SDDMA_IER);
536 writel(descaddr, priv->sdmmc_base + SDDMA_DESPR);
538 writel(0x00, priv->sdmmc_base + SDDMA_CCR);
541 reg_tmp = readl(priv->sdmmc_base + SDDMA_CCR);
542 writel(reg_tmp & DMA_CCR_IF_TO_PERIPHERAL, priv->sdmmc_base +
545 reg_tmp = readl(priv->sdmmc_base + SDDMA_CCR);
546 writel(reg_tmp | DMA_CCR_PERIPHERAL_TO_IF, priv->sdmmc_base +
555 reg_tmp = readl(priv->sdmmc_base + SDDMA_CCR);
556 writel(reg_tmp | DMA_CCR_RUN, priv->sdmmc_base + SDDMA_CCR);
610 reg_tmp = readw(priv->sdmmc_base + SDMMC_BLKLEN);
612 priv->sdmmc_base + SDMMC_BLKLEN);
615 writew(req->data->blocks, priv->sdmmc_base + SDMMC_BLKCNT);
688 busmode = readb(priv->sdmmc_base + SDMMC_BUSMODE);
689 extctrl = readb(priv->sdmmc_base + SDMMC_EXTCTRL);
706 writeb(busmode, priv->sdmmc_base + SDMMC_BUSMODE);
707 writeb(extctrl, priv->sdmmc_base + SDMMC_EXTCTRL);
714 return !(readb(priv->sdmmc_base + SDMMC_STS0) & STS0_WRITE_PROTECT);
720 u32 cd = (readb(priv->sdmmc_base + SDMMC_STS0) & STS0_CD_GPI) >> 3;
813 priv->sdmmc_base = of_iomap(np, 0);
814 if (!priv->sdmmc_base) {
881 iounmap(priv->sdmmc_base);
899 reg_tmp = readb(priv->sdmmc_base + SDMMC_BUSMODE);
900 writel(reg_tmp | BM_SOFT_RESET, priv->sdmmc_base + SDMMC_BUSMODE);
901 reg_tmp = readw(priv->sdmmc_base + SDMMC_BLKLEN);
902 writew(reg_tmp & ~(0xA000), priv->sdmmc_base + SDMMC_BLKLEN);
903 writeb(0xFF, priv->sdmmc_base + SDMMC_STS0);
904 writeb(0xFF, priv->sdmmc_base + SDMMC_STS1);
915 iounmap(priv->sdmmc_base);
941 reg_tmp = readb(priv->sdmmc_base + SDMMC_BUSMODE);
942 writeb(reg_tmp | BM_SOFT_RESET, priv->sdmmc_base +
945 reg_tmp = readw(priv->sdmmc_base + SDMMC_BLKLEN);
946 writew(reg_tmp & 0x5FFF, priv->sdmmc_base + SDMMC_BLKLEN);
948 writeb(0xFF, priv->sdmmc_base + SDMMC_STS0);
949 writeb(0xFF, priv->sdmmc_base + SDMMC_STS1);
965 reg_tmp = readb(priv->sdmmc_base + SDMMC_BUSMODE);
966 writeb(reg_tmp | BM_SOFT_RESET, priv->sdmmc_base +
969 reg_tmp = readw(priv->sdmmc_base + SDMMC_BLKLEN);
971 priv->sdmmc_base + SDMMC_BLKLEN);
973 reg_tmp = readb(priv->sdmmc_base + SDMMC_INTMASK0);
974 writeb(reg_tmp | INT0_DI_INT_EN, priv->sdmmc_base +