Lines Matching defs:reg_tmp
213 u32 reg_tmp = readb(priv->sdmmc_base + SDMMC_BUSMODE);
216 reg_tmp &= ~BM_SD_OFF;
218 reg_tmp |= BM_SD_OFF;
220 writeb(reg_tmp, priv->sdmmc_base + SDMMC_BUSMODE);
248 u32 reg_tmp;
250 reg_tmp = readb(priv->sdmmc_base + SDMMC_CTLR);
251 writeb(reg_tmp | CTLR_CMD_START, priv->sdmmc_base + SDMMC_CTLR);
258 u32 reg_tmp;
268 reg_tmp = readb(priv->sdmmc_base + SDMMC_CTLR);
269 writeb(reg_tmp | CTLR_FIFO_RESET, priv->sdmmc_base + SDMMC_CTLR);
281 reg_tmp = readb(priv->sdmmc_base + SDMMC_CTLR);
282 writeb((reg_tmp & 0x0F) | (cmdtype << 4),
376 u32 reg_tmp;
386 reg_tmp = readb(priv->sdmmc_base + SDMMC_INTMASK0);
387 if ((reg_tmp & INT0_DI_INT_EN) && (status0 & STS0_DEVICE_INS)) {
465 u32 reg_tmp;
470 reg_tmp = readb(priv->sdmmc_base + SDMMC_BUSMODE);
471 writeb(reg_tmp | BM_SOFT_RESET, priv->sdmmc_base + SDMMC_BUSMODE);
474 reg_tmp = readb(priv->sdmmc_base + SDMMC_CTLR);
475 writeb(reg_tmp | CTLR_FIFO_RESET, priv->sdmmc_base + SDMMC_CTLR);
494 reg_tmp = readb(priv->sdmmc_base + SDMMC_STS2);
495 writeb(reg_tmp | STS2_DIS_FORCECLK, priv->sdmmc_base + SDMMC_STS2);
528 u32 reg_tmp;
541 reg_tmp = readl(priv->sdmmc_base + SDDMA_CCR);
542 writel(reg_tmp & DMA_CCR_IF_TO_PERIPHERAL, priv->sdmmc_base +
545 reg_tmp = readl(priv->sdmmc_base + SDDMA_CCR);
546 writel(reg_tmp | DMA_CCR_PERIPHERAL_TO_IF, priv->sdmmc_base +
553 u32 reg_tmp;
555 reg_tmp = readl(priv->sdmmc_base + SDDMA_CCR);
556 writel(reg_tmp | DMA_CCR_RUN, priv->sdmmc_base + SDDMA_CCR);
567 u32 reg_tmp;
610 reg_tmp = readw(priv->sdmmc_base + SDMMC_BLKLEN);
611 writew((reg_tmp & 0xF800) | (req->data->blksz - 1),
893 u32 reg_tmp;
899 reg_tmp = readb(priv->sdmmc_base + SDMMC_BUSMODE);
900 writel(reg_tmp | BM_SOFT_RESET, priv->sdmmc_base + SDMMC_BUSMODE);
901 reg_tmp = readw(priv->sdmmc_base + SDMMC_BLKLEN);
902 writew(reg_tmp & ~(0xA000), priv->sdmmc_base + SDMMC_BLKLEN);
933 u32 reg_tmp;
941 reg_tmp = readb(priv->sdmmc_base + SDMMC_BUSMODE);
942 writeb(reg_tmp | BM_SOFT_RESET, priv->sdmmc_base +
945 reg_tmp = readw(priv->sdmmc_base + SDMMC_BLKLEN);
946 writew(reg_tmp & 0x5FFF, priv->sdmmc_base + SDMMC_BLKLEN);
957 u32 reg_tmp;
965 reg_tmp = readb(priv->sdmmc_base + SDMMC_BUSMODE);
966 writeb(reg_tmp | BM_SOFT_RESET, priv->sdmmc_base +
969 reg_tmp = readw(priv->sdmmc_base + SDMMC_BLKLEN);
970 writew(reg_tmp | (BLKL_GPI_CD | BLKL_INT_ENABLE),
973 reg_tmp = readb(priv->sdmmc_base + SDMMC_INTMASK0);
974 writeb(reg_tmp | INT0_DI_INT_EN, priv->sdmmc_base +