Lines Matching defs:output
234 u32 output;
750 clk_set_phase(host->clk_output, host->cfg->clk_delays[index].output);
1119 [SDXC_CLK_400K] = { .output = 180, .sample = 180 },
1120 [SDXC_CLK_25M] = { .output = 180, .sample = 75 },
1121 [SDXC_CLK_50M] = { .output = 90, .sample = 120 },
1122 [SDXC_CLK_50M_DDR] = { .output = 60, .sample = 120 },
1124 [SDXC_CLK_50M_DDR_8BIT] = { .output = 90, .sample = 180 },
1128 [SDXC_CLK_400K] = { .output = 180, .sample = 180 },
1129 [SDXC_CLK_25M] = { .output = 180, .sample = 75 },
1130 [SDXC_CLK_50M] = { .output = 150, .sample = 120 },
1131 [SDXC_CLK_50M_DDR] = { .output = 54, .sample = 36 },
1132 [SDXC_CLK_50M_DDR_8BIT] = { .output = 72, .sample = 72 },
1220 dev_err(host->dev, "Enable output clk err %d\n", ret);
1297 host->clk_output = devm_clk_get(&pdev->dev, "output");
1299 dev_err(&pdev->dev, "Could not get output clock\n");