Lines Matching defs:ios
718 struct mmc_ios *ios, u32 rate)
736 if (ios->timing != MMC_TIMING_UHS_DDR50 &&
737 ios->timing != MMC_TIMING_MMC_DDR52) {
739 } else if (ios->bus_width == MMC_BUS_WIDTH_8) {
756 struct mmc_ios *ios)
760 u32 rval, clock = ios->clock, div = 1;
770 if (!ios->clock)
782 if (ios->timing == MMC_TIMING_MMC_DDR52 &&
784 ios->bus_width == MMC_BUS_WIDTH_8)) {
838 ret = sunxi_mmc_clk_set_phase(host, ios, rate);
880 static void sunxi_mmc_set_clk(struct sunxi_mmc_host *host, struct mmc_ios *ios)
886 if (ios->timing == MMC_TIMING_UHS_DDR50 ||
887 ios->timing == MMC_TIMING_MMC_DDR52)
893 host->ferror = sunxi_mmc_clk_set_rate(host, ios);
898 struct mmc_ios *ios)
902 switch (ios->power_mode) {
909 ios->vdd);
943 static void sunxi_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
947 sunxi_mmc_card_power(host, ios);
948 sunxi_mmc_set_bus_width(host, ios->bus_width);
949 sunxi_mmc_set_clk(host, ios);
952 static int sunxi_mmc_volt_switch(struct mmc_host *mmc, struct mmc_ios *ios)
958 ret = mmc_regulator_set_vqmmc(mmc, ios);
963 if (mmc->ios.signal_voltage == MMC_SIGNAL_VOLTAGE_330)
1485 sunxi_mmc_set_bus_width(host, mmc->ios.bus_width);
1486 sunxi_mmc_set_clk(host, &mmc->ios);