Lines Matching defs:host
43 #include <linux/mmc/host.h>
258 #define sh_mmcif_host_to_dev(host) (&host->pd->dev)
260 static inline void sh_mmcif_bitset(struct sh_mmcif_host *host,
263 writel(val | readl(host->addr + reg), host->addr + reg);
266 static inline void sh_mmcif_bitclr(struct sh_mmcif_host *host,
269 writel(~val & readl(host->addr + reg), host->addr + reg);
274 struct sh_mmcif_host *host = arg;
275 struct mmc_request *mrq = host->mrq;
276 struct device *dev = sh_mmcif_host_to_dev(host);
284 complete(&host->dma_complete);
287 static void sh_mmcif_start_dma_rx(struct sh_mmcif_host *host)
289 struct mmc_data *data = host->mrq->data;
292 struct dma_chan *chan = host->chan_rx;
293 struct device *dev = sh_mmcif_host_to_dev(host);
300 host->dma_active = true;
307 desc->callback_param = host;
309 sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN);
319 host->chan_rx = NULL;
320 host->dma_active = false;
323 chan = host->chan_tx;
325 host->chan_tx = NULL;
330 sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN);
337 static void sh_mmcif_start_dma_tx(struct sh_mmcif_host *host)
339 struct mmc_data *data = host->mrq->data;
342 struct dma_chan *chan = host->chan_tx;
343 struct device *dev = sh_mmcif_host_to_dev(host);
350 host->dma_active = true;
357 desc->callback_param = host;
359 sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAWEN);
369 host->chan_tx = NULL;
370 host->dma_active = false;
373 chan = host->chan_rx;
375 host->chan_rx = NULL;
380 sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN);
388 sh_mmcif_request_dma_pdata(struct sh_mmcif_host *host, uintptr_t slave_id)
400 static int sh_mmcif_dma_slave_config(struct sh_mmcif_host *host,
407 res = platform_get_resource(host->pd, IORESOURCE_MEM, 0);
421 static void sh_mmcif_request_dma(struct sh_mmcif_host *host)
423 struct device *dev = sh_mmcif_host_to_dev(host);
424 host->dma_active = false;
430 host->chan_tx = sh_mmcif_request_dma_pdata(host,
432 host->chan_rx = sh_mmcif_request_dma_pdata(host,
435 host->chan_tx = dma_request_chan(dev, "tx");
436 if (IS_ERR(host->chan_tx))
437 host->chan_tx = NULL;
438 host->chan_rx = dma_request_chan(dev, "rx");
439 if (IS_ERR(host->chan_rx))
440 host->chan_rx = NULL;
442 dev_dbg(dev, "%s: got channel TX %p RX %p\n", __func__, host->chan_tx,
443 host->chan_rx);
445 if (!host->chan_tx || !host->chan_rx ||
446 sh_mmcif_dma_slave_config(host, host->chan_tx, DMA_MEM_TO_DEV) ||
447 sh_mmcif_dma_slave_config(host, host->chan_rx, DMA_DEV_TO_MEM))
453 if (host->chan_tx)
454 dma_release_channel(host->chan_tx);
455 if (host->chan_rx)
456 dma_release_channel(host->chan_rx);
457 host->chan_tx = host->chan_rx = NULL;
460 static void sh_mmcif_release_dma(struct sh_mmcif_host *host)
462 sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN);
464 if (host->chan_tx) {
465 struct dma_chan *chan = host->chan_tx;
466 host->chan_tx = NULL;
469 if (host->chan_rx) {
470 struct dma_chan *chan = host->chan_rx;
471 host->chan_rx = NULL;
475 host->dma_active = false;
478 static void sh_mmcif_clock_control(struct sh_mmcif_host *host, unsigned int clk)
480 struct device *dev = sh_mmcif_host_to_dev(host);
483 unsigned int current_clk = clk_get_rate(host->clk);
486 sh_mmcif_bitclr(host, MMCIF_CE_CLK_CTRL, CLK_ENABLE);
487 sh_mmcif_bitclr(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR);
492 if (host->clkdiv_map) {
500 if (!((1 << i) & host->clkdiv_map))
509 freq = clk_round_rate(host->clk, clk * div);
524 clk_set_rate(host->clk, best_freq);
532 sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR & clkdiv);
533 sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_ENABLE);
536 static void sh_mmcif_sync_reset(struct sh_mmcif_host *host)
540 tmp = 0x010f0000 & sh_mmcif_readl(host->addr, MMCIF_CE_CLK_CTRL);
542 sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_ON);
543 sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_OFF);
544 if (host->ccs_enable)
546 if (host->clk_ctrl2_enable)
547 sh_mmcif_writel(host->addr, MMCIF_CE_CLK_CTRL2, 0x0F0F0000);
548 sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, tmp |
551 sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_ATYP);
554 static int sh_mmcif_error_manage(struct sh_mmcif_host *host)
556 struct device *dev = sh_mmcif_host_to_dev(host);
560 host->sd_error = false;
562 state1 = sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1);
563 state2 = sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS2);
568 sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, CMD_CTRL_BREAK);
569 sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, ~CMD_CTRL_BREAK);
571 if (!(sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1)
581 sh_mmcif_sync_reset(host);
588 host->state, host->wait_for);
592 host->state, host->wait_for);
596 host->state, host->wait_for);
602 static bool sh_mmcif_next_block(struct sh_mmcif_host *host, u32 *p)
604 struct mmc_data *data = host->mrq->data;
606 host->sg_blkidx += host->blocksize;
608 /* data->sg->length must be a multiple of host->blocksize? */
609 BUG_ON(host->sg_blkidx > data->sg->length);
611 if (host->sg_blkidx == data->sg->length) {
612 host->sg_blkidx = 0;
613 if (++host->sg_idx < data->sg_len)
614 host->pio_ptr = sg_virt(++data->sg);
616 host->pio_ptr = p;
619 return host->sg_idx != data->sg_len;
622 static void sh_mmcif_single_read(struct sh_mmcif_host *host,
625 host->blocksize = (sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) &
628 host->wait_for = MMCIF_WAIT_FOR_READ;
631 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN);
634 static bool sh_mmcif_read_block(struct sh_mmcif_host *host)
636 struct device *dev = sh_mmcif_host_to_dev(host);
637 struct mmc_data *data = host->mrq->data;
641 if (host->sd_error) {
642 data->error = sh_mmcif_error_manage(host);
647 for (i = 0; i < host->blocksize / 4; i++)
648 *p++ = sh_mmcif_readl(host->addr, MMCIF_CE_DATA);
651 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFRE);
652 host->wait_for = MMCIF_WAIT_FOR_READ_END;
657 static void sh_mmcif_multi_read(struct sh_mmcif_host *host,
665 host->blocksize = sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) &
668 host->wait_for = MMCIF_WAIT_FOR_MREAD;
669 host->sg_idx = 0;
670 host->sg_blkidx = 0;
671 host->pio_ptr = sg_virt(data->sg);
673 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN);
676 static bool sh_mmcif_mread_block(struct sh_mmcif_host *host)
678 struct device *dev = sh_mmcif_host_to_dev(host);
679 struct mmc_data *data = host->mrq->data;
680 u32 *p = host->pio_ptr;
683 if (host->sd_error) {
684 data->error = sh_mmcif_error_manage(host);
691 for (i = 0; i < host->blocksize / 4; i++)
692 *p++ = sh_mmcif_readl(host->addr, MMCIF_CE_DATA);
694 if (!sh_mmcif_next_block(host, p))
697 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN);
702 static void sh_mmcif_single_write(struct sh_mmcif_host *host,
705 host->blocksize = (sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) &
708 host->wait_for = MMCIF_WAIT_FOR_WRITE;
711 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN);
714 static bool sh_mmcif_write_block(struct sh_mmcif_host *host)
716 struct device *dev = sh_mmcif_host_to_dev(host);
717 struct mmc_data *data = host->mrq->data;
721 if (host->sd_error) {
722 data->error = sh_mmcif_error_manage(host);
727 for (i = 0; i < host->blocksize / 4; i++)
728 sh_mmcif_writel(host->addr, MMCIF_CE_DATA, *p++);
731 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MDTRANE);
732 host->wait_for = MMCIF_WAIT_FOR_WRITE_END;
737 static void sh_mmcif_multi_write(struct sh_mmcif_host *host,
745 host->blocksize = sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) &
748 host->wait_for = MMCIF_WAIT_FOR_MWRITE;
749 host->sg_idx = 0;
750 host->sg_blkidx = 0;
751 host->pio_ptr = sg_virt(data->sg);
753 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN);
756 static bool sh_mmcif_mwrite_block(struct sh_mmcif_host *host)
758 struct device *dev = sh_mmcif_host_to_dev(host);
759 struct mmc_data *data = host->mrq->data;
760 u32 *p = host->pio_ptr;
763 if (host->sd_error) {
764 data->error = sh_mmcif_error_manage(host);
771 for (i = 0; i < host->blocksize / 4; i++)
772 sh_mmcif_writel(host->addr, MMCIF_CE_DATA, *p++);
774 if (!sh_mmcif_next_block(host, p))
777 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN);
782 static void sh_mmcif_get_response(struct sh_mmcif_host *host,
786 cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP3);
787 cmd->resp[1] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP2);
788 cmd->resp[2] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP1);
789 cmd->resp[3] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP0);
791 cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP0);
794 static void sh_mmcif_get_cmd12response(struct sh_mmcif_host *host,
797 cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP_CMD12);
800 static u32 sh_mmcif_set_cmd(struct sh_mmcif_host *host,
803 struct device *dev = sh_mmcif_host_to_dev(host);
832 switch (host->bus_width) {
846 switch (host->timing) {
849 * MMC core will only set this timing, if the host
865 sh_mmcif_bitset(host, MMCIF_CE_BLOCK_SET,
883 static int sh_mmcif_data_trans(struct sh_mmcif_host *host,
886 struct device *dev = sh_mmcif_host_to_dev(host);
890 sh_mmcif_multi_read(host, mrq);
893 sh_mmcif_multi_write(host, mrq);
896 sh_mmcif_single_write(host, mrq);
900 sh_mmcif_single_read(host, mrq);
908 static void sh_mmcif_start_cmd(struct sh_mmcif_host *host,
921 if (host->ccs_enable)
925 sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET, 0);
926 sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET,
929 opc = sh_mmcif_set_cmd(host, mrq);
931 if (host->ccs_enable)
932 sh_mmcif_writel(host->addr, MMCIF_CE_INT, 0xD80430C0);
934 sh_mmcif_writel(host->addr, MMCIF_CE_INT, 0xD80430C0 | INT_CCS);
935 sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, mask);
937 sh_mmcif_writel(host->addr, MMCIF_CE_ARG, cmd->arg);
939 spin_lock_irqsave(&host->lock, flags);
940 sh_mmcif_writel(host->addr, MMCIF_CE_CMD_SET, opc);
942 host->wait_for = MMCIF_WAIT_FOR_CMD;
943 schedule_delayed_work(&host->timeout_work, host->timeout);
944 spin_unlock_irqrestore(&host->lock, flags);
947 static void sh_mmcif_stop_cmd(struct sh_mmcif_host *host,
950 struct device *dev = sh_mmcif_host_to_dev(host);
954 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MCMD12DRE);
957 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MCMD12RBE);
961 mrq->stop->error = sh_mmcif_error_manage(host);
965 host->wait_for = MMCIF_WAIT_FOR_STOP;
970 struct sh_mmcif_host *host = mmc_priv(mmc);
971 struct device *dev = sh_mmcif_host_to_dev(host);
974 spin_lock_irqsave(&host->lock, flags);
975 if (host->state != STATE_IDLE) {
977 __func__, host->state);
978 spin_unlock_irqrestore(&host->lock, flags);
984 host->state = STATE_REQUEST;
985 spin_unlock_irqrestore(&host->lock, flags);
987 host->mrq = mrq;
989 sh_mmcif_start_cmd(host, mrq);
992 static void sh_mmcif_clk_setup(struct sh_mmcif_host *host)
994 struct device *dev = sh_mmcif_host_to_dev(host);
996 if (host->mmc->f_max) {
999 f_max = host->mmc->f_max;
1001 f_min = clk_round_rate(host->clk, f_min_old / 2);
1010 host->clkdiv_map = 0x3ff;
1012 host->mmc->f_max = f_max / (1 << ffs(host->clkdiv_map));
1013 host->mmc->f_min = f_min / (1 << fls(host->clkdiv_map));
1015 unsigned int clk = clk_get_rate(host->clk);
1017 host->mmc->f_max = clk / 2;
1018 host->mmc->f_min = clk / 512;
1022 host->mmc->f_max, host->mmc->f_min);
1027 struct sh_mmcif_host *host = mmc_priv(mmc);
1028 struct device *dev = sh_mmcif_host_to_dev(host);
1031 spin_lock_irqsave(&host->lock, flags);
1032 if (host->state != STATE_IDLE) {
1034 __func__, host->state);
1035 spin_unlock_irqrestore(&host->lock, flags);
1039 host->state = STATE_IOS;
1040 spin_unlock_irqrestore(&host->lock, flags);
1046 if (!host->power) {
1047 clk_prepare_enable(host->clk);
1049 sh_mmcif_sync_reset(host);
1050 sh_mmcif_request_dma(host);
1051 host->power = true;
1057 if (host->power) {
1058 sh_mmcif_clock_control(host, 0);
1059 sh_mmcif_release_dma(host);
1061 clk_disable_unprepare(host->clk);
1062 host->power = false;
1066 sh_mmcif_clock_control(host, ios->clock);
1070 host->timing = ios->timing;
1071 host->bus_width = ios->bus_width;
1072 host->state = STATE_IDLE;
1081 static bool sh_mmcif_end_cmd(struct sh_mmcif_host *host)
1083 struct mmc_command *cmd = host->mrq->cmd;
1084 struct mmc_data *data = host->mrq->data;
1085 struct device *dev = sh_mmcif_host_to_dev(host);
1088 if (host->sd_error) {
1096 cmd->error = sh_mmcif_error_manage(host);
1101 host->sd_error = false;
1109 sh_mmcif_get_response(host, cmd);
1118 init_completion(&host->dma_complete);
1121 if (host->chan_rx)
1122 sh_mmcif_start_dma_rx(host);
1124 if (host->chan_tx)
1125 sh_mmcif_start_dma_tx(host);
1128 if (!host->dma_active) {
1129 data->error = sh_mmcif_data_trans(host, host->mrq, cmd->opcode);
1134 time = wait_for_completion_interruptible_timeout(&host->dma_complete,
1135 host->timeout);
1138 dma_unmap_sg(host->chan_rx->device->dev,
1142 dma_unmap_sg(host->chan_tx->device->dev,
1146 if (host->sd_error) {
1147 dev_err(host->mmc->parent,
1150 data->error = sh_mmcif_error_manage(host);
1152 dev_err(host->mmc->parent, "DMA timeout!\n");
1155 dev_err(host->mmc->parent,
1159 sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC,
1161 host->dma_active = false;
1167 dmaengine_terminate_all(host->chan_rx);
1169 dmaengine_terminate_all(host->chan_tx);
1177 struct sh_mmcif_host *host = dev_id;
1179 struct device *dev = sh_mmcif_host_to_dev(host);
1184 spin_lock_irqsave(&host->lock, flags);
1185 wait_work = host->wait_for;
1186 spin_unlock_irqrestore(&host->lock, flags);
1188 cancel_delayed_work_sync(&host->timeout_work);
1190 mutex_lock(&host->thread_lock);
1192 mrq = host->mrq;
1195 host->state, host->wait_for);
1196 mutex_unlock(&host->thread_lock);
1207 mutex_unlock(&host->thread_lock);
1211 wait = sh_mmcif_end_cmd(host);
1215 wait = sh_mmcif_mread_block(host);
1219 wait = sh_mmcif_read_block(host);
1223 wait = sh_mmcif_mwrite_block(host);
1227 wait = sh_mmcif_write_block(host);
1230 if (host->sd_error) {
1231 mrq->stop->error = sh_mmcif_error_manage(host);
1235 sh_mmcif_get_cmd12response(host, mrq->stop);
1240 if (host->sd_error) {
1241 mrq->data->error = sh_mmcif_error_manage(host);
1250 schedule_delayed_work(&host->timeout_work, host->timeout);
1252 mutex_unlock(&host->thread_lock);
1256 if (host->wait_for != MMCIF_WAIT_FOR_STOP) {
1263 sh_mmcif_stop_cmd(host, mrq);
1265 schedule_delayed_work(&host->timeout_work, host->timeout);
1266 mutex_unlock(&host->thread_lock);
1272 host->wait_for = MMCIF_WAIT_FOR_REQUEST;
1273 host->state = STATE_IDLE;
1274 host->mrq = NULL;
1275 mmc_request_done(host->mmc, mrq);
1277 mutex_unlock(&host->thread_lock);
1284 struct sh_mmcif_host *host = dev_id;
1285 struct device *dev = sh_mmcif_host_to_dev(host);
1288 state = sh_mmcif_readl(host->addr, MMCIF_CE_INT);
1289 mask = sh_mmcif_readl(host->addr, MMCIF_CE_INT_MASK);
1290 if (host->ccs_enable)
1291 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~(state & mask));
1293 sh_mmcif_writel(host->addr, MMCIF_CE_INT, INT_CCS | ~(state & mask));
1294 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, state & MASK_CLEAN);
1301 host->sd_error = true;
1305 if (!host->mrq)
1307 if (!host->dma_active)
1309 else if (host->sd_error)
1310 sh_mmcif_dma_complete(host);
1321 struct sh_mmcif_host *host = container_of(d, struct sh_mmcif_host, timeout_work);
1322 struct mmc_request *mrq = host->mrq;
1323 struct device *dev = sh_mmcif_host_to_dev(host);
1326 if (host->dying)
1330 spin_lock_irqsave(&host->lock, flags);
1331 if (host->state == STATE_IDLE) {
1332 spin_unlock_irqrestore(&host->lock, flags);
1337 host->wait_for, mrq->cmd->opcode);
1339 host->state = STATE_TIMEOUT;
1340 spin_unlock_irqrestore(&host->lock, flags);
1346 switch (host->wait_for) {
1348 mrq->cmd->error = sh_mmcif_error_manage(host);
1351 mrq->stop->error = sh_mmcif_error_manage(host);
1359 mrq->data->error = sh_mmcif_error_manage(host);
1365 host->state = STATE_IDLE;
1366 host->wait_for = MMCIF_WAIT_FOR_REQUEST;
1367 host->mrq = NULL;
1368 mmc_request_done(host->mmc, mrq);
1371 static void sh_mmcif_init_ocr(struct sh_mmcif_host *host)
1373 struct device *dev = sh_mmcif_host_to_dev(host);
1375 struct mmc_host *mmc = host->mmc;
1392 struct sh_mmcif_host *host;
1415 host = mmc_priv(mmc);
1416 host->mmc = mmc;
1417 host->addr = reg;
1418 host->timeout = msecs_to_jiffies(10000);
1419 host->ccs_enable = true;
1420 host->clk_ctrl2_enable = false;
1422 host->pd = pdev;
1424 spin_lock_init(&host->lock);
1427 sh_mmcif_init_ocr(host);
1441 platform_set_drvdata(pdev, host);
1443 host->clk = devm_clk_get(dev, NULL);
1444 if (IS_ERR(host->clk)) {
1445 ret = PTR_ERR(host->clk);
1450 ret = clk_prepare_enable(host->clk);
1454 sh_mmcif_clk_setup(host);
1457 host->power = false;
1463 INIT_DELAYED_WORK(&host->timeout_work, sh_mmcif_timeout_work);
1465 sh_mmcif_sync_reset(host);
1466 sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL);
1470 sh_mmcif_irqt, 0, name, host);
1478 0, "sh_mmc:int", host);
1485 mutex_init(&host->thread_lock);
1494 sh_mmcif_readl(host->addr, MMCIF_CE_VERSION) & 0xffff,
1495 clk_get_rate(host->clk) / 1000000UL);
1498 clk_disable_unprepare(host->clk);
1502 clk_disable_unprepare(host->clk);
1512 struct sh_mmcif_host *host = platform_get_drvdata(pdev);
1514 host->dying = true;
1515 clk_prepare_enable(host->clk);
1520 mmc_remove_host(host->mmc);
1521 sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL);
1528 cancel_delayed_work_sync(&host->timeout_work);
1530 clk_disable_unprepare(host->clk);
1531 mmc_free_host(host->mmc);
1541 struct sh_mmcif_host *host = dev_get_drvdata(dev);
1544 sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL);