Lines Matching refs:host
3 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
31 #include <linux/mmc/host.h>
41 pr_debug("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x)
44 pr_err("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x)
51 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable);
53 static bool sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd);
55 void sdhci_dumpregs(struct sdhci_host *host)
60 sdhci_readl(host, SDHCI_DMA_ADDRESS),
61 sdhci_readw(host, SDHCI_HOST_VERSION));
63 sdhci_readw(host, SDHCI_BLOCK_SIZE),
64 sdhci_readw(host, SDHCI_BLOCK_COUNT));
66 sdhci_readl(host, SDHCI_ARGUMENT),
67 sdhci_readw(host, SDHCI_TRANSFER_MODE));
69 sdhci_readl(host, SDHCI_PRESENT_STATE),
70 sdhci_readb(host, SDHCI_HOST_CONTROL));
72 sdhci_readb(host, SDHCI_POWER_CONTROL),
73 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
75 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
76 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
78 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
79 sdhci_readl(host, SDHCI_INT_STATUS));
81 sdhci_readl(host, SDHCI_INT_ENABLE),
82 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
84 sdhci_readw(host, SDHCI_AUTO_CMD_STATUS),
85 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
87 sdhci_readl(host, SDHCI_CAPABILITIES),
88 sdhci_readl(host, SDHCI_CAPABILITIES_1));
90 sdhci_readw(host, SDHCI_COMMAND),
91 sdhci_readl(host, SDHCI_MAX_CURRENT));
93 sdhci_readl(host, SDHCI_RESPONSE),
94 sdhci_readl(host, SDHCI_RESPONSE + 4));
96 sdhci_readl(host, SDHCI_RESPONSE + 8),
97 sdhci_readl(host, SDHCI_RESPONSE + 12));
99 sdhci_readw(host, SDHCI_HOST_CONTROL2));
101 if (host->flags & SDHCI_USE_ADMA) {
102 if (host->flags & SDHCI_USE_64_BIT_DMA) {
104 sdhci_readl(host, SDHCI_ADMA_ERROR),
105 sdhci_readl(host, SDHCI_ADMA_ADDRESS_HI),
106 sdhci_readl(host, SDHCI_ADMA_ADDRESS));
109 sdhci_readl(host, SDHCI_ADMA_ERROR),
110 sdhci_readl(host, SDHCI_ADMA_ADDRESS));
114 if (host->ops->dump_vendor_regs)
115 host->ops->dump_vendor_regs(host);
127 static void sdhci_do_enable_v4_mode(struct sdhci_host *host)
131 ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
136 sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2);
140 * This can be called before sdhci_add_host() by Vendor's host controller
143 void sdhci_enable_v4_mode(struct sdhci_host *host)
145 host->v4_mode = true;
146 sdhci_do_enable_v4_mode(host);
155 static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
159 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
160 !mmc_card_is_removable(host->mmc) || mmc_can_gpio_cd(host->mmc))
164 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
167 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
170 host->ier &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
173 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
174 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
177 static void sdhci_enable_card_detection(struct sdhci_host *host)
179 sdhci_set_card_detection(host, true);
182 static void sdhci_disable_card_detection(struct sdhci_host *host)
184 sdhci_set_card_detection(host, false);
187 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
189 if (host->bus_on)
191 host->bus_on = true;
192 pm_runtime_get_noresume(host->mmc->parent);
195 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
197 if (!host->bus_on)
199 host->bus_on = false;
200 pm_runtime_put_noidle(host->mmc->parent);
203 void sdhci_reset(struct sdhci_host *host, u8 mask)
207 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
210 host->clock = 0;
212 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
213 sdhci_runtime_pm_bus_off(host);
223 if (!(sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask))
227 mmc_hostname(host->mmc), (int)mask);
228 sdhci_dumpregs(host);
236 static void sdhci_do_reset(struct sdhci_host *host, u8 mask)
238 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
239 struct mmc_host *mmc = host->mmc;
245 host->ops->reset(host, mask);
248 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
249 if (host->ops->enable_dma)
250 host->ops->enable_dma(host);
254 host->preset_enabled = false;
258 static void sdhci_set_default_irqs(struct sdhci_host *host)
260 host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
266 if (host->tuning_mode == SDHCI_TUNING_MODE_2 ||
267 host->tuning_mode == SDHCI_TUNING_MODE_3)
268 host->ier |= SDHCI_INT_RETUNE;
270 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
271 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
274 static void sdhci_config_dma(struct sdhci_host *host)
279 if (host->version < SDHCI_SPEC_200)
282 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
290 if (!(host->flags & SDHCI_REQ_USE_DMA))
294 if (host->flags & SDHCI_USE_ADMA)
297 if (host->flags & SDHCI_USE_64_BIT_DMA) {
303 if (host->v4_mode) {
304 ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
306 sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2);
307 } else if (host->flags & SDHCI_USE_ADMA) {
317 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
320 static void sdhci_init(struct sdhci_host *host, int soft)
322 struct mmc_host *mmc = host->mmc;
326 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
328 sdhci_do_reset(host, SDHCI_RESET_ALL);
330 if (host->v4_mode)
331 sdhci_do_enable_v4_mode(host);
333 spin_lock_irqsave(&host->lock, flags);
334 sdhci_set_default_irqs(host);
335 spin_unlock_irqrestore(&host->lock, flags);
337 host->cqe_on = false;
341 host->clock = 0;
342 host->reinit_uhs = true;
347 static void sdhci_reinit(struct sdhci_host *host)
349 u32 cd = host->ier & (SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
351 sdhci_init(host, 0);
352 sdhci_enable_card_detection(host);
357 * been missed while the host controller was being reset, so trigger a
360 if (cd != (host->ier & (SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT)))
361 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
364 static void __sdhci_led_activate(struct sdhci_host *host)
368 if (host->quirks & SDHCI_QUIRK_NO_LED)
371 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
373 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
376 static void __sdhci_led_deactivate(struct sdhci_host *host)
380 if (host->quirks & SDHCI_QUIRK_NO_LED)
383 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
385 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
392 struct sdhci_host *host = container_of(led, struct sdhci_host, led);
395 spin_lock_irqsave(&host->lock, flags);
397 if (host->runtime_suspended)
401 __sdhci_led_deactivate(host);
403 __sdhci_led_activate(host);
405 spin_unlock_irqrestore(&host->lock, flags);
408 static int sdhci_led_register(struct sdhci_host *host)
410 struct mmc_host *mmc = host->mmc;
412 if (host->quirks & SDHCI_QUIRK_NO_LED)
415 snprintf(host->led_name, sizeof(host->led_name),
418 host->led.name = host->led_name;
419 host->led.brightness = LED_OFF;
420 host->led.default_trigger = mmc_hostname(mmc);
421 host->led.brightness_set = sdhci_led_control;
423 return led_classdev_register(mmc_dev(mmc), &host->led);
426 static void sdhci_led_unregister(struct sdhci_host *host)
428 if (host->quirks & SDHCI_QUIRK_NO_LED)
431 led_classdev_unregister(&host->led);
434 static inline void sdhci_led_activate(struct sdhci_host *host)
438 static inline void sdhci_led_deactivate(struct sdhci_host *host)
444 static inline int sdhci_led_register(struct sdhci_host *host)
449 static inline void sdhci_led_unregister(struct sdhci_host *host)
453 static inline void sdhci_led_activate(struct sdhci_host *host)
455 __sdhci_led_activate(host);
458 static inline void sdhci_led_deactivate(struct sdhci_host *host)
460 __sdhci_led_deactivate(host);
465 static void sdhci_mod_timer(struct sdhci_host *host, struct mmc_request *mrq,
469 mod_timer(&host->data_timer, timeout);
471 mod_timer(&host->timer, timeout);
474 static void sdhci_del_timer(struct sdhci_host *host, struct mmc_request *mrq)
477 del_timer(&host->data_timer);
479 del_timer(&host->timer);
482 static inline bool sdhci_has_requests(struct sdhci_host *host)
484 return host->cmd || host->data_cmd;
493 static void sdhci_read_block_pio(struct sdhci_host *host)
502 blksize = host->data->blksz;
508 BUG_ON(!sg_miter_next(&host->sg_miter));
510 len = min(host->sg_miter.length, blksize);
513 host->sg_miter.consumed = len;
515 buf = host->sg_miter.addr;
519 scratch = sdhci_readl(host, SDHCI_BUFFER);
532 sg_miter_stop(&host->sg_miter);
537 static void sdhci_write_block_pio(struct sdhci_host *host)
546 blksize = host->data->blksz;
553 BUG_ON(!sg_miter_next(&host->sg_miter));
555 len = min(host->sg_miter.length, blksize);
558 host->sg_miter.consumed = len;
560 buf = host->sg_miter.addr;
570 sdhci_writel(host, scratch, SDHCI_BUFFER);
577 sg_miter_stop(&host->sg_miter);
582 static void sdhci_transfer_pio(struct sdhci_host *host)
586 if (host->blocks == 0)
589 if (host->data->flags & MMC_DATA_READ)
599 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
600 (host->data->blocks == 1))
603 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
604 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
607 if (host->data->flags & MMC_DATA_READ)
608 sdhci_read_block_pio(host);
610 sdhci_write_block_pio(host);
612 host->blocks--;
613 if (host->blocks == 0)
620 static int sdhci_pre_dma_transfer(struct sdhci_host *host,
633 if (host->bounce_buffer) {
636 if (length > host->bounce_buffer_size) {
638 mmc_hostname(host->mmc), length,
639 host->bounce_buffer_size);
644 if (host->ops->copy_to_bounce_buffer) {
645 host->ops->copy_to_bounce_buffer(host,
649 host->bounce_buffer, length);
653 dma_sync_single_for_device(host->mmc->parent,
654 host->bounce_addr,
655 host->bounce_buffer_size,
661 sg_count = dma_map_sg(mmc_dev(host->mmc),
687 void sdhci_adma_write_desc(struct sdhci_host *host, void **desc,
697 if (host->flags & SDHCI_USE_64_BIT_DMA)
700 *desc += host->desc_sz;
704 static inline void __sdhci_adma_write_desc(struct sdhci_host *host,
708 if (host->ops->adma_write_desc)
709 host->ops->adma_write_desc(host, desc, addr, len, cmd);
711 sdhci_adma_write_desc(host, desc, addr, len, cmd);
722 static void sdhci_adma_table_pre(struct sdhci_host *host,
737 host->sg_count = sg_count;
739 desc = host->adma_table;
740 align = host->align_buffer;
742 align_addr = host->align_addr;
744 for_each_sg(data->sg, sg, host->sg_count, i) {
764 __sdhci_adma_write_desc(host, &desc, align_addr,
782 while (len > host->max_adma) {
785 __sdhci_adma_write_desc(host, &desc, addr, n, ADMA2_TRAN_VALID);
792 __sdhci_adma_write_desc(host, &desc, addr, len,
799 WARN_ON((desc - host->adma_table) >= host->adma_table_sz);
802 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
804 if (desc != host->adma_table) {
805 desc -= host->desc_sz;
810 __sdhci_adma_write_desc(host, &desc, 0, 0, ADMA2_NOP_END_VALID);
814 static void sdhci_adma_table_post(struct sdhci_host *host,
827 for_each_sg(data->sg, sg, host->sg_count, i)
834 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
837 align = host->align_buffer;
839 for_each_sg(data->sg, sg, host->sg_count, i) {
855 static void sdhci_set_adma_addr(struct sdhci_host *host, dma_addr_t addr)
857 sdhci_writel(host, lower_32_bits(addr), SDHCI_ADMA_ADDRESS);
858 if (host->flags & SDHCI_USE_64_BIT_DMA)
859 sdhci_writel(host, upper_32_bits(addr), SDHCI_ADMA_ADDRESS_HI);
862 static dma_addr_t sdhci_sdma_address(struct sdhci_host *host)
864 if (host->bounce_buffer)
865 return host->bounce_addr;
867 return sg_dma_address(host->data->sg);
870 static void sdhci_set_sdma_addr(struct sdhci_host *host, dma_addr_t addr)
872 if (host->v4_mode)
873 sdhci_set_adma_addr(host, addr);
875 sdhci_writel(host, addr, SDHCI_DMA_ADDRESS);
878 static unsigned int sdhci_target_timeout(struct sdhci_host *host,
889 if (host->clock && data->timeout_clks) {
894 * host->clock is in Hz. target_timeout is in us.
898 if (do_div(val, host->clock))
907 static void sdhci_calc_sw_timeout(struct sdhci_host *host,
911 struct mmc_host *mmc = host->mmc;
919 target_timeout = sdhci_target_timeout(host, cmd, data);
924 freq = host->mmc->actual_clock ? : host->clock;
930 host->data_timeout = data->blocks * target_timeout +
933 host->data_timeout = target_timeout;
936 if (host->data_timeout)
937 host->data_timeout += MMC_CMD_TRANSFER_TIME;
940 static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd,
950 * If the host controller provides us with an incorrect timeout
955 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
968 target_timeout = sdhci_target_timeout(host, cmd, data);
976 * (2) host->timeout_clk < 2^16
981 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
990 if (!(host->quirks2 & SDHCI_QUIRK2_DISABLE_HW_TIMEOUT))
1001 static void sdhci_set_transfer_irqs(struct sdhci_host *host)
1006 if (host->flags & SDHCI_REQ_USE_DMA)
1007 host->ier = (host->ier & ~pio_irqs) | dma_irqs;
1009 host->ier = (host->ier & ~dma_irqs) | pio_irqs;
1011 if (host->flags & (SDHCI_AUTO_CMD23 | SDHCI_AUTO_CMD12))
1012 host->ier |= SDHCI_INT_AUTO_CMD_ERR;
1014 host->ier &= ~SDHCI_INT_AUTO_CMD_ERR;
1016 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1017 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
1020 void sdhci_set_data_timeout_irq(struct sdhci_host *host, bool enable)
1023 host->ier |= SDHCI_INT_DATA_TIMEOUT;
1025 host->ier &= ~SDHCI_INT_DATA_TIMEOUT;
1026 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1027 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
1031 void __sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
1034 u8 count = sdhci_calc_timeout(host, cmd, &too_big);
1037 host->quirks2 & SDHCI_QUIRK2_DISABLE_HW_TIMEOUT) {
1038 sdhci_calc_sw_timeout(host, cmd);
1039 sdhci_set_data_timeout_irq(host, false);
1040 } else if (!(host->ier & SDHCI_INT_DATA_TIMEOUT)) {
1041 sdhci_set_data_timeout_irq(host, true);
1044 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
1048 static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
1050 if (host->ops->set_timeout)
1051 host->ops->set_timeout(host, cmd);
1053 __sdhci_set_timeout(host, cmd);
1056 static void sdhci_initialize_data(struct sdhci_host *host,
1059 WARN_ON(host->data);
1063 BUG_ON(data->blksz > host->mmc->max_blk_size);
1066 host->data = data;
1067 host->data_early = 0;
1068 host->data->bytes_xfered = 0;
1071 static inline void sdhci_set_block_info(struct sdhci_host *host,
1075 sdhci_writew(host,
1076 SDHCI_MAKE_BLKSZ(host->sdma_boundary, data->blksz),
1082 if (host->version >= SDHCI_SPEC_410 && host->v4_mode &&
1083 (host->quirks2 & SDHCI_QUIRK2_USE_32BIT_BLK_CNT)) {
1084 if (sdhci_readw(host, SDHCI_BLOCK_COUNT))
1085 sdhci_writew(host, 0, SDHCI_BLOCK_COUNT);
1086 sdhci_writew(host, data->blocks, SDHCI_32BIT_BLK_CNT);
1088 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
1092 static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
1096 sdhci_initialize_data(host, data);
1098 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
1103 host->flags |= SDHCI_REQ_USE_DMA;
1114 if (host->flags & SDHCI_USE_ADMA) {
1115 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE) {
1125 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
1127 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
1136 host->flags &= ~SDHCI_REQ_USE_DMA;
1141 host->flags &= ~SDHCI_REQ_USE_DMA;
1148 sdhci_config_dma(host);
1150 if (host->flags & SDHCI_REQ_USE_DMA) {
1151 int sg_cnt = sdhci_pre_dma_transfer(host, data, COOKIE_MAPPED);
1159 host->flags &= ~SDHCI_REQ_USE_DMA;
1160 } else if (host->flags & SDHCI_USE_ADMA) {
1161 sdhci_adma_table_pre(host, data, sg_cnt);
1162 sdhci_set_adma_addr(host, host->adma_addr);
1165 sdhci_set_sdma_addr(host, sdhci_sdma_address(host));
1169 if (!(host->flags & SDHCI_REQ_USE_DMA)) {
1173 if (host->data->flags & MMC_DATA_READ)
1177 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
1178 host->blocks = data->blocks;
1181 sdhci_set_transfer_irqs(host);
1183 sdhci_set_block_info(host, data);
1188 static int sdhci_external_dma_init(struct sdhci_host *host)
1191 struct mmc_host *mmc = host->mmc;
1193 host->tx_chan = dma_request_chan(mmc->parent, "tx");
1194 if (IS_ERR(host->tx_chan)) {
1195 ret = PTR_ERR(host->tx_chan);
1198 host->tx_chan = NULL;
1202 host->rx_chan = dma_request_chan(mmc->parent, "rx");
1203 if (IS_ERR(host->rx_chan)) {
1204 if (host->tx_chan) {
1205 dma_release_channel(host->tx_chan);
1206 host->tx_chan = NULL;
1209 ret = PTR_ERR(host->rx_chan);
1212 host->rx_chan = NULL;
1218 static struct dma_chan *sdhci_external_dma_channel(struct sdhci_host *host,
1221 return data->flags & MMC_DATA_WRITE ? host->tx_chan : host->rx_chan;
1224 static int sdhci_external_dma_setup(struct sdhci_host *host,
1236 if (!host->mapbase)
1240 cfg.src_addr = host->mapbase + SDHCI_BUFFER;
1241 cfg.dst_addr = host->mapbase + SDHCI_BUFFER;
1253 chan = sdhci_external_dma_channel(host, data);
1259 sg_cnt = sdhci_pre_dma_transfer(host, data, COOKIE_MAPPED);
1279 static void sdhci_external_dma_release(struct sdhci_host *host)
1281 if (host->tx_chan) {
1282 dma_release_channel(host->tx_chan);
1283 host->tx_chan = NULL;
1286 if (host->rx_chan) {
1287 dma_release_channel(host->rx_chan);
1288 host->rx_chan = NULL;
1291 sdhci_switch_external_dma(host, false);
1294 static void __sdhci_external_dma_prepare_data(struct sdhci_host *host,
1299 sdhci_initialize_data(host, data);
1301 host->flags |= SDHCI_REQ_USE_DMA;
1302 sdhci_set_transfer_irqs(host);
1304 sdhci_set_block_info(host, data);
1307 static void sdhci_external_dma_prepare_data(struct sdhci_host *host,
1310 if (!sdhci_external_dma_setup(host, cmd)) {
1311 __sdhci_external_dma_prepare_data(host, cmd);
1313 sdhci_external_dma_release(host);
1315 mmc_hostname(host->mmc));
1316 sdhci_prepare_data(host, cmd);
1320 static void sdhci_external_dma_pre_transfer(struct sdhci_host *host,
1328 chan = sdhci_external_dma_channel(host, cmd->data);
1335 static inline int sdhci_external_dma_init(struct sdhci_host *host)
1340 static inline void sdhci_external_dma_release(struct sdhci_host *host)
1344 static inline void sdhci_external_dma_prepare_data(struct sdhci_host *host,
1351 static inline void sdhci_external_dma_pre_transfer(struct sdhci_host *host,
1356 static inline struct dma_chan *sdhci_external_dma_channel(struct sdhci_host *host,
1364 void sdhci_switch_external_dma(struct sdhci_host *host, bool en)
1366 host->use_external_dma = en;
1370 static inline bool sdhci_auto_cmd12(struct sdhci_host *host,
1373 return !mrq->sbc && (host->flags & SDHCI_AUTO_CMD12) &&
1377 static inline bool sdhci_auto_cmd23(struct sdhci_host *host,
1380 return mrq->sbc && (host->flags & SDHCI_AUTO_CMD23);
1383 static inline bool sdhci_manual_cmd23(struct sdhci_host *host,
1386 return mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23);
1389 static inline void sdhci_auto_cmd_select(struct sdhci_host *host,
1393 bool use_cmd12 = sdhci_auto_cmd12(host, cmd->mrq) &&
1395 bool use_cmd23 = sdhci_auto_cmd23(host, cmd->mrq);
1404 if (host->version >= SDHCI_SPEC_410 && host->v4_mode &&
1408 ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1413 sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2);
1428 static void sdhci_set_transfer_mode(struct sdhci_host *host,
1435 if (host->quirks2 &
1439 sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE);
1442 mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
1443 sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 |
1449 WARN_ON(!host->data);
1451 if (!(host->quirks2 & SDHCI_QUIRK2_SUPPORT_SINGLE))
1456 sdhci_auto_cmd_select(host, cmd, &mode);
1457 if (sdhci_auto_cmd23(host, cmd->mrq))
1458 sdhci_writel(host, cmd->mrq->sbc->arg, SDHCI_ARGUMENT2);
1463 if (host->flags & SDHCI_REQ_USE_DMA)
1466 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
1469 static bool sdhci_needs_reset(struct sdhci_host *host, struct mmc_request *mrq)
1471 return (!(host->flags & SDHCI_DEVICE_DEAD) &&
1475 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST)));
1478 static void sdhci_set_mrq_done(struct sdhci_host *host, struct mmc_request *mrq)
1483 if (host->mrqs_done[i] == mrq) {
1490 if (!host->mrqs_done[i]) {
1491 host->mrqs_done[i] = mrq;
1499 static void __sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request *mrq)
1501 if (host->cmd && host->cmd->mrq == mrq)
1502 host->cmd = NULL;
1504 if (host->data_cmd && host->data_cmd->mrq == mrq)
1505 host->data_cmd = NULL;
1507 if (host->deferred_cmd && host->deferred_cmd->mrq == mrq)
1508 host->deferred_cmd = NULL;
1510 if (host->data && host->data->mrq == mrq)
1511 host->data = NULL;
1513 if (sdhci_needs_reset(host, mrq))
1514 host->pending_reset = true;
1516 sdhci_set_mrq_done(host, mrq);
1518 sdhci_del_timer(host, mrq);
1520 if (!sdhci_has_requests(host))
1521 sdhci_led_deactivate(host);
1524 static void sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request *mrq)
1526 __sdhci_finish_mrq(host, mrq);
1528 queue_work(host->complete_wq, &host->complete_work);
1531 static void __sdhci_finish_data(struct sdhci_host *host, bool sw_data_timeout)
1533 struct mmc_command *data_cmd = host->data_cmd;
1534 struct mmc_data *data = host->data;
1536 host->data = NULL;
1537 host->data_cmd = NULL;
1544 if (!host->cmd || host->cmd == data_cmd)
1545 sdhci_do_reset(host, SDHCI_RESET_CMD);
1546 sdhci_do_reset(host, SDHCI_RESET_DATA);
1549 if ((host->flags & (SDHCI_REQ_USE_DMA | SDHCI_USE_ADMA)) ==
1551 sdhci_adma_table_post(host, data);
1571 ((!data->mrq->sbc && !sdhci_auto_cmd12(host, data->mrq)) ||
1579 __sdhci_finish_mrq(host, data->mrq);
1582 host->cmd = NULL;
1583 if (!sdhci_send_command(host, data->stop)) {
1590 __sdhci_finish_mrq(host, data->mrq);
1592 WARN_ON(host->deferred_cmd);
1593 host->deferred_cmd = data->stop;
1598 __sdhci_finish_mrq(host, data->mrq);
1602 static void sdhci_finish_data(struct sdhci_host *host)
1604 __sdhci_finish_data(host, false);
1607 static bool sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
1613 WARN_ON(host->cmd);
1618 if ((host->quirks2 & SDHCI_QUIRK2_STOP_WITH_TC) &&
1631 if (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask)
1634 host->cmd = cmd;
1635 host->data_timeout = 0;
1637 WARN_ON(host->data_cmd);
1638 host->data_cmd = cmd;
1639 sdhci_set_timeout(host, cmd);
1643 if (host->use_external_dma)
1644 sdhci_external_dma_prepare_data(host, cmd);
1646 sdhci_prepare_data(host, cmd);
1649 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
1651 sdhci_set_transfer_mode(host, cmd);
1683 if (host->data_timeout)
1684 timeout += nsecs_to_jiffies(host->data_timeout);
1689 sdhci_mod_timer(host, cmd->mrq, timeout);
1691 if (host->use_external_dma)
1692 sdhci_external_dma_pre_transfer(host, cmd);
1694 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
1699 static bool sdhci_present_error(struct sdhci_host *host,
1702 if (!present || host->flags & SDHCI_DEVICE_DEAD) {
1710 static bool sdhci_send_command_retry(struct sdhci_host *host,
1713 __releases(host->lock)
1714 __acquires(host->lock)
1716 struct mmc_command *deferred_cmd = host->deferred_cmd;
1720 while (!sdhci_send_command(host, cmd)) {
1723 mmc_hostname(host->mmc));
1724 sdhci_dumpregs(host);
1729 spin_unlock_irqrestore(&host->lock, flags);
1733 present = host->mmc->ops->get_cd(host->mmc);
1735 spin_lock_irqsave(&host->lock, flags);
1738 if (cmd == deferred_cmd && cmd != host->deferred_cmd)
1741 if (sdhci_present_error(host, cmd, present))
1745 if (cmd == host->deferred_cmd)
1746 host->deferred_cmd = NULL;
1751 static void sdhci_read_rsp_136(struct sdhci_host *host, struct mmc_command *cmd)
1757 cmd->resp[i] = sdhci_readl(host, reg);
1760 if (host->quirks2 & SDHCI_QUIRK2_RSP_136_HAS_CRC)
1771 static void sdhci_finish_command(struct sdhci_host *host)
1773 struct mmc_command *cmd = host->cmd;
1775 host->cmd = NULL;
1779 sdhci_read_rsp_136(host, cmd);
1781 cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
1786 mmc_command_done(host->mmc, cmd->mrq);
1789 * The host can send and interrupt when the busy state has
1801 } else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ) &&
1802 cmd == host->data_cmd) {
1810 if (!sdhci_send_command(host, cmd->mrq->cmd)) {
1811 WARN_ON(host->deferred_cmd);
1812 host->deferred_cmd = cmd->mrq->cmd;
1817 if (host->data && host->data_early)
1818 sdhci_finish_data(host);
1821 __sdhci_finish_mrq(host, cmd->mrq);
1825 static u16 sdhci_get_preset_value(struct sdhci_host *host)
1829 switch (host->timing) {
1832 preset = sdhci_readw(host, SDHCI_PRESET_FOR_HIGH_SPEED);
1835 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1838 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25);
1841 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50);
1845 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104);
1849 preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50);
1852 preset = sdhci_readw(host, SDHCI_PRESET_FOR_HS400);
1856 mmc_hostname(host->mmc));
1857 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1863 u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock,
1871 if (host->version >= SDHCI_SPEC_300) {
1872 if (host->preset_enabled) {
1875 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1876 pre_val = sdhci_get_preset_value(host);
1878 if (host->clk_mul &&
1882 clk_mul = host->clk_mul;
1893 if (host->clk_mul) {
1895 if ((host->max_clk * host->clk_mul / div)
1899 if ((host->max_clk * host->clk_mul / div) <= clock) {
1906 clk_mul = host->clk_mul;
1917 if (!host->clk_mul || switch_base_clk) {
1919 if (host->max_clk <= clock)
1924 if ((host->max_clk / div) <= clock)
1930 if ((host->quirks2 & SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN)
1931 && !div && host->max_clk <= 25000000)
1937 if ((host->max_clk / div) <= clock)
1946 *actual_clock = (host->max_clk * clk_mul) / real_div;
1955 void sdhci_enable_clk(struct sdhci_host *host, u16 clk)
1960 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1967 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1972 mmc_hostname(host->mmc));
1973 sdhci_dumpregs(host);
1979 if (host->version >= SDHCI_SPEC_410 && host->v4_mode) {
1982 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1989 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1994 mmc_hostname(host->mmc));
1995 sdhci_dumpregs(host);
2003 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
2007 void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
2011 host->mmc->actual_clock = 0;
2013 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
2018 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
2019 sdhci_enable_clk(host, clk);
2023 static void sdhci_set_power_reg(struct sdhci_host *host, unsigned char mode,
2026 struct mmc_host *mmc = host->mmc;
2031 sdhci_writeb(host, SDHCI_POWER_ON, SDHCI_POWER_CONTROL);
2033 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
2036 void sdhci_set_power_noreg(struct sdhci_host *host, unsigned char mode,
2069 mmc_hostname(host->mmc), vdd);
2074 if (host->pwr == pwr)
2077 host->pwr = pwr;
2080 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
2081 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
2082 sdhci_runtime_pm_bus_off(host);
2088 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
2089 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
2096 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
2097 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
2101 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
2103 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
2104 sdhci_runtime_pm_bus_on(host);
2110 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
2116 void sdhci_set_power(struct sdhci_host *host, unsigned char mode,
2119 if (IS_ERR(host->mmc->supply.vmmc))
2120 sdhci_set_power_noreg(host, mode, vdd);
2122 sdhci_set_power_reg(host, mode, vdd);
2132 void sdhci_set_power_and_bus_voltage(struct sdhci_host *host,
2136 if (!IS_ERR(host->mmc->supply.vmmc)) {
2137 struct mmc_host *mmc = host->mmc;
2141 sdhci_set_power_noreg(host, mode, vdd);
2153 struct sdhci_host *host = mmc_priv(mmc);
2161 spin_lock_irqsave(&host->lock, flags);
2163 sdhci_led_activate(host);
2165 if (sdhci_present_error(host, mrq->cmd, present))
2168 cmd = sdhci_manual_cmd23(host, mrq) ? mrq->sbc : mrq->cmd;
2170 if (!sdhci_send_command_retry(host, cmd, flags))
2173 spin_unlock_irqrestore(&host->lock, flags);
2178 sdhci_finish_mrq(host, mrq);
2179 spin_unlock_irqrestore(&host->lock, flags);
2185 struct sdhci_host *host = mmc_priv(mmc);
2190 spin_lock_irqsave(&host->lock, flags);
2192 if (sdhci_present_error(host, mrq->cmd, true)) {
2193 sdhci_finish_mrq(host, mrq);
2197 cmd = sdhci_manual_cmd23(host, mrq) ? mrq->sbc : mrq->cmd;
2206 if (!sdhci_send_command(host, cmd))
2209 sdhci_led_activate(host);
2212 spin_unlock_irqrestore(&host->lock, flags);
2217 void sdhci_set_bus_width(struct sdhci_host *host, int width)
2221 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
2226 if (host->mmc->caps & MMC_CAP_8_BIT_DATA)
2233 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
2237 void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
2241 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2242 /* Select Bus Speed Mode for host */
2258 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
2276 static bool sdhci_preset_needed(struct sdhci_host *host, unsigned char timing)
2278 return !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) &&
2282 static bool sdhci_presetable_values_change(struct sdhci_host *host, struct mmc_ios *ios)
2289 return !host->preset_enabled &&
2290 (sdhci_preset_needed(host, ios->timing) || host->drv_type != ios->drv_type);
2295 struct sdhci_host *host = mmc_priv(mmc);
2296 bool reinit_uhs = host->reinit_uhs;
2300 host->reinit_uhs = false;
2305 if (host->flags & SDHCI_DEVICE_DEAD) {
2317 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
2318 sdhci_reinit(host);
2321 if (host->version >= SDHCI_SPEC_300 &&
2323 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN))
2324 sdhci_enable_preset_value(host, false);
2326 if (!ios->clock || ios->clock != host->clock) {
2327 turning_on_clk = ios->clock && !host->clock;
2329 host->ops->set_clock(host, ios->clock);
2330 host->clock = ios->clock;
2332 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK &&
2333 host->clock) {
2334 host->timeout_clk = host->mmc->actual_clock ?
2335 host->mmc->actual_clock / 1000 :
2336 host->clock / 1000;
2337 host->mmc->max_busy_timeout =
2338 host->ops->get_max_timeout_count ?
2339 host->ops->get_max_timeout_count(host) :
2341 host->mmc->max_busy_timeout /= host->timeout_clk;
2345 if (host->ops->set_power)
2346 host->ops->set_power(host, ios->power_mode, ios->vdd);
2348 sdhci_set_power(host, ios->power_mode, ios->vdd);
2350 if (host->ops->platform_send_init_74_clocks)
2351 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
2353 host->ops->set_bus_width(host, ios->bus_width);
2361 host->timing == ios->timing &&
2362 host->version >= SDHCI_SPEC_300 &&
2363 !sdhci_presetable_values_change(host, ios))
2366 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
2368 if (!(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT)) {
2383 if (host->version >= SDHCI_SPEC_300) {
2386 if (!host->preset_enabled) {
2387 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
2392 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2408 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
2409 host->drv_type = ios->drv_type;
2419 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
2421 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
2423 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
2426 host->ops->set_clock(host, host->clock);
2430 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
2432 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
2434 host->ops->set_uhs_signaling(host, ios->timing);
2435 host->timing = ios->timing;
2437 if (sdhci_preset_needed(host, ios->timing)) {
2440 sdhci_enable_preset_value(host, true);
2441 preset = sdhci_get_preset_value(host);
2444 host->drv_type = ios->drv_type;
2448 host->ops->set_clock(host, host->clock);
2450 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
2457 if (host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
2458 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
2464 struct sdhci_host *host = mmc_priv(mmc);
2467 if (host->flags & SDHCI_DEVICE_DEAD)
2471 if (!mmc_card_is_removable(host->mmc))
2482 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
2486 return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
2489 static int sdhci_check_ro(struct sdhci_host *host)
2494 spin_lock_irqsave(&host->lock, flags);
2496 if (host->flags & SDHCI_DEVICE_DEAD)
2498 else if (host->ops->get_ro)
2499 is_readonly = host->ops->get_ro(host);
2500 else if (mmc_can_gpio_ro(host->mmc))
2501 is_readonly = mmc_gpio_get_ro(host->mmc);
2503 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
2506 spin_unlock_irqrestore(&host->lock, flags);
2509 return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
2517 struct sdhci_host *host = mmc_priv(mmc);
2520 if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
2521 return sdhci_check_ro(host);
2525 if (sdhci_check_ro(host)) {
2536 struct sdhci_host *host = mmc_priv(mmc);
2538 if (host->ops && host->ops->hw_reset)
2539 host->ops->hw_reset(host);
2542 static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
2544 if (!(host->flags & SDHCI_DEVICE_DEAD)) {
2546 host->ier |= SDHCI_INT_CARD_INT;
2548 host->ier &= ~SDHCI_INT_CARD_INT;
2550 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2551 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2557 struct sdhci_host *host = mmc_priv(mmc);
2561 pm_runtime_get_noresume(host->mmc->parent);
2563 spin_lock_irqsave(&host->lock, flags);
2564 sdhci_enable_sdio_irq_nolock(host, enable);
2565 spin_unlock_irqrestore(&host->lock, flags);
2568 pm_runtime_put_noidle(host->mmc->parent);
2574 struct sdhci_host *host = mmc_priv(mmc);
2577 spin_lock_irqsave(&host->lock, flags);
2578 sdhci_enable_sdio_irq_nolock(host, true);
2579 spin_unlock_irqrestore(&host->lock, flags);
2585 struct sdhci_host *host = mmc_priv(mmc);
2593 if (host->version < SDHCI_SPEC_300)
2596 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2600 if (!(host->flags & SDHCI_SIGNALING_330))
2604 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2618 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2627 if (!(host->flags & SDHCI_SIGNALING_180))
2643 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2646 if (host->ops->voltage_switch)
2647 host->ops->voltage_switch(host);
2650 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2659 if (!(host->flags & SDHCI_SIGNALING_120))
2679 struct sdhci_host *host = mmc_priv(mmc);
2683 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
2690 struct sdhci_host *host = mmc_priv(mmc);
2693 spin_lock_irqsave(&host->lock, flags);
2694 host->flags |= SDHCI_HS400_TUNING;
2695 spin_unlock_irqrestore(&host->lock, flags);
2700 void sdhci_start_tuning(struct sdhci_host *host)
2704 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2706 if (host->quirks2 & SDHCI_QUIRK2_TUNING_WORK_AROUND)
2708 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2720 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
2721 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
2725 void sdhci_end_tuning(struct sdhci_host *host)
2727 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2728 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2732 void sdhci_reset_tuning(struct sdhci_host *host)
2736 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2739 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2743 void sdhci_abort_tuning(struct sdhci_host *host, u32 opcode)
2745 sdhci_reset_tuning(host);
2747 sdhci_do_reset(host, SDHCI_RESET_CMD);
2748 sdhci_do_reset(host, SDHCI_RESET_DATA);
2750 sdhci_end_tuning(host);
2752 mmc_abort_tuning(host->mmc, opcode);
2763 void sdhci_send_tuning(struct sdhci_host *host, u32 opcode)
2765 struct mmc_host *mmc = host->mmc;
2769 u32 b = host->sdma_boundary;
2771 spin_lock_irqsave(&host->lock, flags);
2785 sdhci_writew(host, SDHCI_MAKE_BLKSZ(b, 128), SDHCI_BLOCK_SIZE);
2787 sdhci_writew(host, SDHCI_MAKE_BLKSZ(b, 64), SDHCI_BLOCK_SIZE);
2790 * The tuning block is sent by the card to the host controller.
2795 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
2797 if (!sdhci_send_command_retry(host, &cmd, flags)) {
2798 spin_unlock_irqrestore(&host->lock, flags);
2799 host->tuning_done = 0;
2803 host->cmd = NULL;
2805 sdhci_del_timer(host, &mrq);
2807 host->tuning_done = 0;
2809 spin_unlock_irqrestore(&host->lock, flags);
2812 wait_event_timeout(host->buf_ready_int, (host->tuning_done == 1),
2818 static int __sdhci_execute_tuning(struct sdhci_host *host, u32 opcode)
2826 for (i = 0; i < host->tuning_loop_count; i++) {
2829 sdhci_send_tuning(host, opcode);
2831 if (!host->tuning_done) {
2833 mmc_hostname(host->mmc));
2834 sdhci_abort_tuning(host, opcode);
2839 if (host->tuning_delay > 0)
2840 mdelay(host->tuning_delay);
2842 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2852 mmc_hostname(host->mmc));
2853 sdhci_reset_tuning(host);
2859 struct sdhci_host *host = mmc_priv(mmc);
2864 hs400_tuning = host->flags & SDHCI_HS400_TUNING;
2866 if (host->tuning_mode == SDHCI_TUNING_MODE_1)
2867 tuning_count = host->tuning_count;
2876 switch (host->timing) {
2896 if (host->flags & SDHCI_SDR50_NEEDS_TUNING)
2904 if (host->ops->platform_execute_tuning) {
2905 err = host->ops->platform_execute_tuning(host, opcode);
2909 host->mmc->retune_period = tuning_count;
2911 if (host->tuning_delay < 0)
2912 host->tuning_delay = opcode == MMC_SEND_TUNING_BLOCK;
2914 sdhci_start_tuning(host);
2916 host->tuning_err = __sdhci_execute_tuning(host, opcode);
2918 sdhci_end_tuning(host);
2920 host->flags &= ~SDHCI_HS400_TUNING;
2926 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable)
2929 if (host->version < SDHCI_SPEC_300)
2936 if (host->preset_enabled != enable) {
2937 u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2944 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2947 host->flags |= SDHCI_PV_ENABLED;
2949 host->flags &= ~SDHCI_PV_ENABLED;
2951 host->preset_enabled = enable;
2958 struct sdhci_host *host = mmc_priv(mmc);
2962 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
2970 struct sdhci_host *host = mmc_priv(mmc);
2979 if (host->flags & SDHCI_REQ_USE_DMA && !host->bounce_buffer)
2980 sdhci_pre_dma_transfer(host, mrq->data, COOKIE_PRE_MAPPED);
2983 static void sdhci_error_out_mrqs(struct sdhci_host *host, int err)
2985 if (host->data_cmd) {
2986 host->data_cmd->error = err;
2987 sdhci_finish_mrq(host, host->data_cmd->mrq);
2990 if (host->cmd) {
2991 host->cmd->error = err;
2992 sdhci_finish_mrq(host, host->cmd->mrq);
2998 struct sdhci_host *host = mmc_priv(mmc);
3003 if (host->ops->card_event)
3004 host->ops->card_event(host);
3008 spin_lock_irqsave(&host->lock, flags);
3011 if (sdhci_has_requests(host) && !present) {
3013 mmc_hostname(host->mmc));
3015 mmc_hostname(host->mmc));
3017 sdhci_do_reset(host, SDHCI_RESET_CMD);
3018 sdhci_do_reset(host, SDHCI_RESET_DATA);
3020 sdhci_error_out_mrqs(host, -ENOMEDIUM);
3023 spin_unlock_irqrestore(&host->lock, flags);
3049 static bool sdhci_request_done(struct sdhci_host *host)
3055 spin_lock_irqsave(&host->lock, flags);
3058 mrq = host->mrqs_done[i];
3064 spin_unlock_irqrestore(&host->lock, flags);
3072 if (sdhci_needs_reset(host, mrq)) {
3076 * also be in mrqs_done, otherwise host->cmd and host->data_cmd
3079 if (host->cmd || host->data_cmd) {
3080 spin_unlock_irqrestore(&host->lock, flags);
3085 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)
3087 host->ops->set_clock(host, host->clock);
3093 sdhci_do_reset(host, SDHCI_RESET_CMD);
3094 sdhci_do_reset(host, SDHCI_RESET_DATA);
3096 host->pending_reset = false;
3104 if (host->flags & SDHCI_REQ_USE_DMA) {
3107 if (host->use_external_dma && data &&
3109 struct dma_chan *chan = sdhci_external_dma_channel(host, data);
3111 host->mrqs_done[i] = NULL;
3112 spin_unlock_irqrestore(&host->lock, flags);
3114 spin_lock_irqsave(&host->lock, flags);
3115 sdhci_set_mrq_done(host, mrq);
3119 if (host->bounce_buffer) {
3127 if (length > host->bounce_buffer_size) {
3129 mmc_hostname(host->mmc),
3130 host->bounce_buffer_size,
3133 length = host->bounce_buffer_size;
3136 host->mmc->parent,
3137 host->bounce_addr,
3138 host->bounce_buffer_size,
3142 host->bounce_buffer,
3147 host->mmc->parent,
3148 host->bounce_addr,
3149 host->bounce_buffer_size,
3154 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
3162 host->mrqs_done[i] = NULL;
3164 spin_unlock_irqrestore(&host->lock, flags);
3166 if (host->ops->request_done)
3167 host->ops->request_done(host, mrq);
3169 mmc_request_done(host->mmc, mrq);
3176 struct sdhci_host *host = container_of(work, struct sdhci_host,
3179 while (!sdhci_request_done(host))
3185 struct sdhci_host *host;
3188 host = from_timer(host, t, timer);
3190 spin_lock_irqsave(&host->lock, flags);
3192 if (host->cmd && !sdhci_data_line_cmd(host->cmd)) {
3194 mmc_hostname(host->mmc));
3195 sdhci_dumpregs(host);
3197 host->cmd->error = -ETIMEDOUT;
3198 sdhci_finish_mrq(host, host->cmd->mrq);
3201 spin_unlock_irqrestore(&host->lock, flags);
3206 struct sdhci_host *host;
3209 host = from_timer(host, t, data_timer);
3211 spin_lock_irqsave(&host->lock, flags);
3213 if (host->data || host->data_cmd ||
3214 (host->cmd && sdhci_data_line_cmd(host->cmd))) {
3216 mmc_hostname(host->mmc));
3217 sdhci_dumpregs(host);
3219 if (host->data) {
3220 host->data->error = -ETIMEDOUT;
3221 __sdhci_finish_data(host, true);
3222 queue_work(host->complete_wq, &host->complete_work);
3223 } else if (host->data_cmd) {
3224 host->data_cmd->error = -ETIMEDOUT;
3225 sdhci_finish_mrq(host, host->data_cmd->mrq);
3227 host->cmd->error = -ETIMEDOUT;
3228 sdhci_finish_mrq(host, host->cmd->mrq);
3232 spin_unlock_irqrestore(&host->lock, flags);
3241 static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask, u32 *intmask_p)
3244 if (intmask & SDHCI_INT_AUTO_CMD_ERR && host->data_cmd) {
3245 struct mmc_request *mrq = host->data_cmd->mrq;
3246 u16 auto_cmd_status = sdhci_readw(host, SDHCI_AUTO_CMD_STATUS);
3252 if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
3258 if (!host->cmd) {
3264 if (host->pending_reset)
3267 mmc_hostname(host->mmc), (unsigned)intmask);
3268 sdhci_dumpregs(host);
3275 host->cmd->error = -ETIMEDOUT;
3277 host->cmd->error = -EILSEQ;
3280 if (host->cmd->data &&
3283 host->cmd = NULL;
3288 __sdhci_finish_mrq(host, host->cmd->mrq);
3294 struct mmc_request *mrq = host->cmd->mrq;
3295 u16 auto_cmd_status = sdhci_readw(host, SDHCI_AUTO_CMD_STATUS);
3300 if (mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
3302 __sdhci_finish_mrq(host, mrq);
3308 sdhci_finish_command(host);
3311 static void sdhci_adma_show_error(struct sdhci_host *host)
3313 void *desc = host->adma_table;
3314 dma_addr_t dma = host->adma_addr;
3316 sdhci_dumpregs(host);
3321 if (host->flags & SDHCI_USE_64_BIT_DMA)
3335 desc += host->desc_sz;
3336 dma += host->desc_sz;
3343 static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
3349 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND));
3352 host->tuning_done = 1;
3353 wake_up(&host->buf_ready_int);
3358 if (!host->data) {
3359 struct mmc_command *data_cmd = host->data_cmd;
3368 host->data_cmd = NULL;
3370 __sdhci_finish_mrq(host, data_cmd->mrq);
3374 host->data_cmd = NULL;
3380 if (host->cmd == data_cmd)
3383 __sdhci_finish_mrq(host, data_cmd->mrq);
3393 if (host->pending_reset)
3397 mmc_hostname(host->mmc), (unsigned)intmask);
3398 sdhci_dumpregs(host);
3404 host->data->error = -ETIMEDOUT;
3406 host->data->error = -EILSEQ;
3408 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
3410 host->data->error = -EILSEQ;
3412 pr_err("%s: ADMA error: 0x%08x\n", mmc_hostname(host->mmc),
3414 sdhci_adma_show_error(host);
3415 host->data->error = -EIO;
3416 if (host->ops->adma_workaround)
3417 host->ops->adma_workaround(host, intmask);
3420 if (host->data->error)
3421 sdhci_finish_data(host);
3424 sdhci_transfer_pio(host);
3431 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
3438 dmastart = sdhci_sdma_address(host);
3439 dmanow = dmastart + host->data->bytes_xfered;
3446 host->data->bytes_xfered = dmanow - dmastart;
3448 &dmastart, host->data->bytes_xfered, &dmanow);
3449 sdhci_set_sdma_addr(host, dmanow);
3453 if (host->cmd == host->data_cmd) {
3459 host->data_early = 1;
3461 sdhci_finish_data(host);
3467 static inline bool sdhci_defer_done(struct sdhci_host *host,
3472 return host->pending_reset || host->always_defer_done ||
3473 ((host->flags & SDHCI_REQ_USE_DMA) && data &&
3481 struct sdhci_host *host = dev_id;
3486 spin_lock(&host->lock);
3488 if (host->runtime_suspended) {
3489 spin_unlock(&host->lock);
3493 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
3502 if (host->ops->irq) {
3503 intmask = host->ops->irq(host, intmask);
3511 sdhci_writel(host, mask, SDHCI_INT_STATUS);
3514 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
3528 host->ier &= ~(SDHCI_INT_CARD_INSERT |
3530 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
3532 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
3533 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
3535 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
3538 host->thread_isr |= intmask & (SDHCI_INT_CARD_INSERT |
3544 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK, &intmask);
3547 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
3551 mmc_hostname(host->mmc));
3554 mmc_retune_needed(host->mmc);
3557 (host->ier & SDHCI_INT_CARD_INT)) {
3558 sdhci_enable_sdio_irq_nolock(host, false);
3559 sdio_signal_irq(host->mmc);
3569 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
3575 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
3580 struct mmc_request *mrq = host->mrqs_done[i];
3585 if (sdhci_defer_done(host, mrq)) {
3589 host->mrqs_done[i] = NULL;
3593 if (host->deferred_cmd)
3596 spin_unlock(&host->lock);
3603 if (host->ops->request_done)
3604 host->ops->request_done(host, mrqs_done[i]);
3606 mmc_request_done(host->mmc, mrqs_done[i]);
3611 mmc_hostname(host->mmc), unexpected);
3612 sdhci_dumpregs(host);
3620 struct sdhci_host *host = dev_id;
3625 while (!sdhci_request_done(host))
3628 spin_lock_irqsave(&host->lock, flags);
3630 isr = host->thread_isr;
3631 host->thread_isr = 0;
3633 cmd = host->deferred_cmd;
3634 if (cmd && !sdhci_send_command_retry(host, cmd, flags))
3635 sdhci_finish_mrq(host, cmd->mrq);
3637 spin_unlock_irqrestore(&host->lock, flags);
3640 struct mmc_host *mmc = host->mmc;
3657 static bool sdhci_cd_irq_can_wakeup(struct sdhci_host *host)
3659 return mmc_card_is_removable(host->mmc) &&
3660 !(host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
3661 !mmc_can_gpio_cd(host->mmc);
3672 static bool sdhci_enable_irq_wakeups(struct sdhci_host *host)
3680 if (sdhci_cd_irq_can_wakeup(host)) {
3685 if (mmc_card_wake_sdio_irq(host->mmc)) {
3693 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
3696 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
3698 sdhci_writel(host, irq_val, SDHCI_INT_ENABLE);
3700 host->irq_wake_enabled = !enable_irq_wake(host->irq);
3702 return host->irq_wake_enabled;
3705 static void sdhci_disable_irq_wakeups(struct sdhci_host *host)
3711 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
3713 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
3715 disable_irq_wake(host->irq);
3717 host->irq_wake_enabled = false;
3720 int sdhci_suspend_host(struct sdhci_host *host)
3722 sdhci_disable_card_detection(host);
3724 mmc_retune_timer_stop(host->mmc);
3726 if (!device_may_wakeup(mmc_dev(host->mmc)) ||
3727 !sdhci_enable_irq_wakeups(host)) {
3728 host->ier = 0;
3729 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3730 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
3731 free_irq(host->irq, host);
3739 int sdhci_resume_host(struct sdhci_host *host)
3741 struct mmc_host *mmc = host->mmc;
3744 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
3745 if (host->ops->enable_dma)
3746 host->ops->enable_dma(host);
3749 if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) &&
3750 (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) {
3751 /* Card keeps power but host controller does not */
3752 sdhci_init(host, 0);
3753 host->pwr = 0;
3754 host->clock = 0;
3755 host->reinit_uhs = true;
3758 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
3761 if (host->irq_wake_enabled) {
3762 sdhci_disable_irq_wakeups(host);
3764 ret = request_threaded_irq(host->irq, sdhci_irq,
3766 mmc_hostname(host->mmc), host);
3771 sdhci_enable_card_detection(host);
3778 int sdhci_runtime_suspend_host(struct sdhci_host *host)
3782 mmc_retune_timer_stop(host->mmc);
3784 spin_lock_irqsave(&host->lock, flags);
3785 host->ier &= SDHCI_INT_CARD_INT;
3786 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
3787 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
3788 spin_unlock_irqrestore(&host->lock, flags);
3790 synchronize_hardirq(host->irq);
3792 spin_lock_irqsave(&host->lock, flags);
3793 host->runtime_suspended = true;
3794 spin_unlock_irqrestore(&host->lock, flags);
3800 int sdhci_runtime_resume_host(struct sdhci_host *host, int soft_reset)
3802 struct mmc_host *mmc = host->mmc;
3804 int host_flags = host->flags;
3807 if (host->ops->enable_dma)
3808 host->ops->enable_dma(host);
3811 sdhci_init(host, soft_reset);
3816 host->pwr = 0;
3817 host->clock = 0;
3818 host->reinit_uhs = true;
3823 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) {
3824 spin_lock_irqsave(&host->lock, flags);
3825 sdhci_enable_preset_value(host, true);
3826 spin_unlock_irqrestore(&host->lock, flags);
3834 spin_lock_irqsave(&host->lock, flags);
3836 host->runtime_suspended = false;
3840 sdhci_enable_sdio_irq_nolock(host, true);
3843 sdhci_enable_card_detection(host);
3845 spin_unlock_irqrestore(&host->lock, flags);
3861 struct sdhci_host *host = mmc_priv(mmc);
3865 spin_lock_irqsave(&host->lock, flags);
3867 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
3874 if (host->v4_mode && (host->caps1 & SDHCI_CAN_DO_ADMA3))
3876 else if (host->flags & SDHCI_USE_64_BIT_DMA)
3880 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
3882 sdhci_writew(host, SDHCI_MAKE_BLKSZ(host->sdma_boundary, 512),
3886 sdhci_set_timeout(host, NULL);
3888 host->ier = host->cqe_ier;
3890 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
3891 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
3893 host->cqe_on = true;
3896 mmc_hostname(mmc), host->ier,
3897 sdhci_readl(host, SDHCI_INT_STATUS));
3899 spin_unlock_irqrestore(&host->lock, flags);
3905 struct sdhci_host *host = mmc_priv(mmc);
3908 spin_lock_irqsave(&host->lock, flags);
3910 sdhci_set_default_irqs(host);
3912 host->cqe_on = false;
3915 sdhci_do_reset(host, SDHCI_RESET_CMD);
3916 sdhci_do_reset(host, SDHCI_RESET_DATA);
3920 mmc_hostname(mmc), host->ier,
3921 sdhci_readl(host, SDHCI_INT_STATUS));
3923 spin_unlock_irqrestore(&host->lock, flags);
3927 bool sdhci_cqe_irq(struct sdhci_host *host, u32 intmask, int *cmd_error,
3932 if (!host->cqe_on)
3952 mask = intmask & host->cqe_ier;
3953 sdhci_writel(host, mask, SDHCI_INT_STATUS);
3957 mmc_hostname(host->mmc));
3959 intmask &= ~(host->cqe_ier | SDHCI_INT_ERROR);
3961 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
3963 mmc_hostname(host->mmc), intmask);
3964 sdhci_dumpregs(host);
3981 struct sdhci_host *host;
3989 host = mmc_priv(mmc);
3990 host->mmc = mmc;
3991 host->mmc_host_ops = sdhci_ops;
3992 mmc->ops = &host->mmc_host_ops;
3994 host->flags = SDHCI_SIGNALING_330;
3996 host->cqe_ier = SDHCI_CQE_INT_MASK;
3997 host->cqe_err_ier = SDHCI_CQE_INT_ERR_MASK;
3999 host->tuning_delay = -1;
4000 host->tuning_loop_count = MAX_TUNING_LOOP;
4002 host->sdma_boundary = SDHCI_DEFAULT_BOUNDARY_ARG;
4009 host->adma_table_cnt = SDHCI_MAX_SEGS * 2 + 1;
4010 host->max_adma = 65536;
4012 return host;
4017 static int sdhci_set_dma_mask(struct sdhci_host *host)
4019 struct mmc_host *mmc = host->mmc;
4023 if (host->quirks2 & SDHCI_QUIRK2_BROKEN_64_BIT_DMA)
4024 host->flags &= ~SDHCI_USE_64_BIT_DMA;
4027 if (host->flags & SDHCI_USE_64_BIT_DMA) {
4032 host->flags &= ~SDHCI_USE_64_BIT_DMA;
4047 void __sdhci_read_caps(struct sdhci_host *host, const u16 *ver,
4054 if (host->read_caps)
4057 host->read_caps = true;
4060 host->quirks = debug_quirks;
4063 host->quirks2 = debug_quirks2;
4065 sdhci_do_reset(host, SDHCI_RESET_ALL);
4067 if (host->v4_mode)
4068 sdhci_do_enable_v4_mode(host);
4070 device_property_read_u64_array(mmc_dev(host->mmc),
4072 device_property_read_u64_array(mmc_dev(host->mmc),
4075 v = ver ? *ver : sdhci_readw(host, SDHCI_HOST_VERSION);
4076 host->version = (v & SDHCI_SPEC_VER_MASK) >> SDHCI_SPEC_VER_SHIFT;
4078 if (host->quirks & SDHCI_QUIRK_MISSING_CAPS)
4082 host->caps = *caps;
4084 host->caps = sdhci_readl(host, SDHCI_CAPABILITIES);
4085 host->caps &= ~lower_32_bits(dt_caps_mask);
4086 host->caps |= lower_32_bits(dt_caps);
4089 if (host->version < SDHCI_SPEC_300)
4093 host->caps1 = *caps1;
4095 host->caps1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
4096 host->caps1 &= ~upper_32_bits(dt_caps_mask);
4097 host->caps1 |= upper_32_bits(dt_caps);
4102 static void sdhci_allocate_bounce_buffer(struct sdhci_host *host)
4104 struct mmc_host *mmc = host->mmc;
4129 host->bounce_buffer = devm_kmalloc(mmc->parent,
4132 if (!host->bounce_buffer) {
4143 host->bounce_addr = dma_map_single(mmc->parent,
4144 host->bounce_buffer,
4147 ret = dma_mapping_error(mmc->parent, host->bounce_addr);
4151 host->bounce_buffer_size = bounce_size;
4162 static inline bool sdhci_can_64bit_dma(struct sdhci_host *host)
4169 if (host->version >= SDHCI_SPEC_410 && host->v4_mode)
4170 return host->caps & SDHCI_CAN_64BIT_V4;
4172 return host->caps & SDHCI_CAN_64BIT;
4175 int sdhci_setup_host(struct sdhci_host *host)
4185 WARN_ON(host == NULL);
4186 if (host == NULL)
4189 mmc = host->mmc;
4193 * early before resetting the host and reading the capabilities so that
4194 * the host can take the appropriate action if regulators are not
4205 sdhci_readw(host, SDHCI_HOST_VERSION),
4206 sdhci_readl(host, SDHCI_PRESENT_STATE));
4208 sdhci_readl(host, SDHCI_CAPABILITIES),
4209 sdhci_readl(host, SDHCI_CAPABILITIES_1));
4211 sdhci_read_caps(host);
4213 override_timeout_clk = host->timeout_clk;
4215 if (host->version > SDHCI_SPEC_420) {
4217 mmc_hostname(mmc), host->version);
4220 if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
4221 host->flags |= SDHCI_USE_SDMA;
4222 else if (!(host->caps & SDHCI_CAN_DO_SDMA))
4225 host->flags |= SDHCI_USE_SDMA;
4227 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
4228 (host->flags & SDHCI_USE_SDMA)) {
4230 host->flags &= ~SDHCI_USE_SDMA;
4233 if ((host->version >= SDHCI_SPEC_200) &&
4234 (host->caps & SDHCI_CAN_DO_ADMA2))
4235 host->flags |= SDHCI_USE_ADMA;
4237 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
4238 (host->flags & SDHCI_USE_ADMA)) {
4240 host->flags &= ~SDHCI_USE_ADMA;
4243 if (sdhci_can_64bit_dma(host))
4244 host->flags |= SDHCI_USE_64_BIT_DMA;
4246 if (host->use_external_dma) {
4247 ret = sdhci_external_dma_init(host);
4255 sdhci_switch_external_dma(host, false);
4258 host->flags &= ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
4261 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
4262 if (host->ops->set_dma_mask)
4263 ret = host->ops->set_dma_mask(host);
4265 ret = sdhci_set_dma_mask(host);
4267 if (!ret && host->ops->enable_dma)
4268 ret = host->ops->enable_dma(host);
4273 host->flags &= ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
4280 if ((host->flags & SDHCI_USE_64_BIT_DMA) && !host->v4_mode)
4281 host->flags &= ~SDHCI_USE_SDMA;
4283 if (host->flags & SDHCI_USE_ADMA) {
4287 if (!(host->flags & SDHCI_USE_64_BIT_DMA))
4288 host->alloc_desc_sz = SDHCI_ADMA2_32_DESC_SZ;
4289 else if (!host->alloc_desc_sz)
4290 host->alloc_desc_sz = SDHCI_ADMA2_64_DESC_SZ(host);
4292 host->desc_sz = host->alloc_desc_sz;
4293 host->adma_table_sz = host->adma_table_cnt * host->desc_sz;
4295 host->align_buffer_sz = SDHCI_MAX_SEGS * SDHCI_ADMA2_ALIGN;
4301 host->align_buffer_sz + host->adma_table_sz,
4306 host->flags &= ~SDHCI_USE_ADMA;
4307 } else if ((dma + host->align_buffer_sz) &
4311 host->flags &= ~SDHCI_USE_ADMA;
4312 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
4313 host->adma_table_sz, buf, dma);
4315 host->align_buffer = buf;
4316 host->align_addr = dma;
4318 host->adma_table = buf + host->align_buffer_sz;
4319 host->adma_addr = dma + host->align_buffer_sz;
4328 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
4329 host->dma_mask = DMA_BIT_MASK(64);
4330 mmc_dev(mmc)->dma_mask = &host->dma_mask;
4333 if (host->version >= SDHCI_SPEC_300)
4334 host->max_clk = FIELD_GET(SDHCI_CLOCK_V3_BASE_MASK, host->caps);
4336 host->max_clk = FIELD_GET(SDHCI_CLOCK_BASE_MASK, host->caps);
4338 host->max_clk *= 1000000;
4339 if (host->max_clk == 0 || host->quirks &
4341 if (!host->ops->get_max_clock) {
4347 host->max_clk = host->ops->get_max_clock(host);
4354 host->clk_mul = FIELD_GET(SDHCI_CLOCK_MUL_MASK, host->caps1);
4362 if (host->clk_mul)
4363 host->clk_mul += 1;
4366 * Set host parameters.
4368 max_clk = host->max_clk;
4370 if (host->ops->get_min_clock)
4371 mmc->f_min = host->ops->get_min_clock(host);
4372 else if (host->version >= SDHCI_SPEC_300) {
4373 if (host->clk_mul)
4374 max_clk = host->max_clk * host->clk_mul;
4379 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
4381 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
4386 if (!(host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
4387 host->timeout_clk = FIELD_GET(SDHCI_TIMEOUT_CLK_MASK, host->caps);
4389 if (host->caps & SDHCI_TIMEOUT_CLK_UNIT)
4390 host->timeout_clk *= 1000;
4392 if (host->timeout_clk == 0) {
4393 if (!host->ops->get_timeout_clock) {
4400 host->timeout_clk =
4401 DIV_ROUND_UP(host->ops->get_timeout_clock(host),
4406 host->timeout_clk = override_timeout_clk;
4408 mmc->max_busy_timeout = host->ops->get_max_timeout_count ?
4409 host->ops->get_max_timeout_count(host) : 1 << 27;
4410 mmc->max_busy_timeout /= host->timeout_clk;
4413 if (host->quirks2 & SDHCI_QUIRK2_DISABLE_HW_TIMEOUT &&
4414 !host->ops->get_max_timeout_count)
4420 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
4421 host->flags |= SDHCI_AUTO_CMD12;
4427 if ((host->version >= SDHCI_SPEC_300) &&
4428 ((host->flags & SDHCI_USE_ADMA) ||
4429 !(host->flags & SDHCI_USE_SDMA) || host->v4_mode) &&
4430 !(host->quirks2 & SDHCI_QUIRK2_ACMD23_BROKEN)) {
4431 host->flags |= SDHCI_AUTO_CMD23;
4444 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
4447 if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23)
4450 if (host->caps & SDHCI_CAN_DO_HISPD)
4453 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
4455 mmc_gpio_get_cd(host->mmc) < 0)
4461 host->sdhci_core_to_disable_vqmmc = !ret;
4467 host->caps1 &= ~(SDHCI_SUPPORT_SDR104 |
4474 host->flags &= ~SDHCI_SIGNALING_330;
4484 if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V) {
4485 host->caps1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
4500 if (host->caps1 & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
4505 if (host->caps1 & SDHCI_SUPPORT_SDR104) {
4510 if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200))
4512 } else if (host->caps1 & SDHCI_SUPPORT_SDR50) {
4516 if (host->quirks2 & SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 &&
4517 (host->caps1 & SDHCI_SUPPORT_HS400))
4526 if ((host->caps1 & SDHCI_SUPPORT_DDR50) &&
4527 !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50))
4530 /* Does the host need tuning for SDR50? */
4531 if (host->caps1 & SDHCI_USE_SDR50_TUNING)
4532 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
4534 /* Driver Type(s) (A, C, D) supported by the host */
4535 if (host->caps1 & SDHCI_DRIVER_TYPE_A)
4537 if (host->caps1 & SDHCI_DRIVER_TYPE_C)
4539 if (host->caps1 & SDHCI_DRIVER_TYPE_D)
4543 host->tuning_count = FIELD_GET(SDHCI_RETUNING_TIMER_COUNT_MASK,
4544 host->caps1);
4550 if (host->tuning_count)
4551 host->tuning_count = 1 << (host->tuning_count - 1);
4554 host->tuning_mode = FIELD_GET(SDHCI_RETUNING_MODE_MASK, host->caps1);
4565 max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
4582 if (host->caps & SDHCI_CAN_VDD_330) {
4589 if (host->caps & SDHCI_CAN_VDD_300) {
4596 if (host->caps & SDHCI_CAN_VDD_180) {
4604 /* If OCR set by host, use it instead. */
4605 if (host->ocr_mask)
4606 ocr_avail = host->ocr_mask;
4614 if (host->ocr_avail_sdio)
4615 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
4617 if (host->ocr_avail_sd)
4618 mmc->ocr_avail_sd &= host->ocr_avail_sd;
4622 if (host->ocr_avail_mmc)
4623 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
4636 host->flags |= SDHCI_SIGNALING_180;
4639 host->flags |= SDHCI_SIGNALING_120;
4641 spin_lock_init(&host->lock);
4654 if (host->flags & SDHCI_USE_ADMA) {
4656 } else if (host->flags & SDHCI_USE_SDMA) {
4673 if (host->flags & SDHCI_USE_ADMA) {
4674 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC) {
4675 host->max_adma = 65532; /* 32-bit alignment */
4688 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
4691 mmc->max_blk_size = (host->caps & SDHCI_MAX_BLOCK_MASK) >>
4705 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
4709 sdhci_allocate_bounce_buffer(host);
4714 if (host->sdhci_core_to_disable_vqmmc)
4717 if (host->align_buffer)
4718 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
4719 host->adma_table_sz, host->align_buffer,
4720 host->align_addr);
4721 host->adma_table = NULL;
4722 host->align_buffer = NULL;
4728 void sdhci_cleanup_host(struct sdhci_host *host)
4730 struct mmc_host *mmc = host->mmc;
4732 if (host->sdhci_core_to_disable_vqmmc)
4735 if (host->align_buffer)
4736 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
4737 host->adma_table_sz, host->align_buffer,
4738 host->align_addr);
4740 if (host->use_external_dma)
4741 sdhci_external_dma_release(host);
4743 host->adma_table = NULL;
4744 host->align_buffer = NULL;
4748 int __sdhci_add_host(struct sdhci_host *host)
4751 struct mmc_host *mmc = host->mmc;
4755 (host->quirks & SDHCI_QUIRK_BROKEN_CQE)) {
4760 host->complete_wq = alloc_workqueue("sdhci", flags, 0);
4761 if (!host->complete_wq)
4764 INIT_WORK(&host->complete_work, sdhci_complete_work);
4766 timer_setup(&host->timer, sdhci_timeout_timer, 0);
4767 timer_setup(&host->data_timer, sdhci_timeout_data_timer, 0);
4769 init_waitqueue_head(&host->buf_ready_int);
4771 sdhci_init(host, 0);
4773 ret = request_threaded_irq(host->irq, sdhci_irq, sdhci_thread_irq,
4774 IRQF_SHARED, mmc_hostname(mmc), host);
4777 mmc_hostname(mmc), host->irq, ret);
4781 ret = sdhci_led_register(host);
4793 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
4794 host->use_external_dma ? "External DMA" :
4795 (host->flags & SDHCI_USE_ADMA) ?
4796 (host->flags & SDHCI_USE_64_BIT_DMA) ? "ADMA 64-bit" : "ADMA" :
4797 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
4799 sdhci_enable_card_detection(host);
4804 sdhci_led_unregister(host);
4806 sdhci_do_reset(host, SDHCI_RESET_ALL);
4807 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
4808 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
4809 free_irq(host->irq, host);
4811 destroy_workqueue(host->complete_wq);
4817 int sdhci_add_host(struct sdhci_host *host)
4821 ret = sdhci_setup_host(host);
4825 ret = __sdhci_add_host(host);
4832 sdhci_cleanup_host(host);
4838 void sdhci_remove_host(struct sdhci_host *host, int dead)
4840 struct mmc_host *mmc = host->mmc;
4844 spin_lock_irqsave(&host->lock, flags);
4846 host->flags |= SDHCI_DEVICE_DEAD;
4848 if (sdhci_has_requests(host)) {
4851 sdhci_error_out_mrqs(host, -ENOMEDIUM);
4854 spin_unlock_irqrestore(&host->lock, flags);
4857 sdhci_disable_card_detection(host);
4861 sdhci_led_unregister(host);
4864 sdhci_do_reset(host, SDHCI_RESET_ALL);
4866 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
4867 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
4868 free_irq(host->irq, host);
4870 del_timer_sync(&host->timer);
4871 del_timer_sync(&host->data_timer);
4873 destroy_workqueue(host->complete_wq);
4875 if (host->sdhci_core_to_disable_vqmmc)
4878 if (host->align_buffer)
4879 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
4880 host->adma_table_sz, host->align_buffer,
4881 host->align_addr);
4883 if (host->use_external_dma)
4884 sdhci_external_dma_release(host);
4886 host->adma_table = NULL;
4887 host->align_buffer = NULL;
4892 void sdhci_free_host(struct sdhci_host *host)
4894 mmc_free_host(host->mmc);