Lines Matching defs:host
157 void (*set_soc_pad)(struct sdhci_host *host,
200 static int xenon_alloc_emmc_phy(struct sdhci_host *host)
202 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
206 params = devm_kzalloc(mmc_dev(host->mmc), sizeof(*params), GFP_KERNEL);
227 static int xenon_emmc_phy_init(struct sdhci_host *host)
231 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
235 reg = sdhci_readl(host, phy_regs->timing_adj);
237 sdhci_writel(host, reg, phy_regs->timing_adj);
255 clock = host->clock;
262 /* wait for host eMMC PHY init completes */
265 reg = sdhci_readl(host, phy_regs->timing_adj);
268 dev_err(mmc_dev(host->mmc), "eMMC PHY init cannot complete after %d us\n",
279 static void armada_3700_soc_pad_voltage_set(struct sdhci_host *host,
282 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
301 static void xenon_emmc_phy_set_soc_pad(struct sdhci_host *host,
304 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
312 params->pad_ctrl.set_soc_pad(host, signal_voltage);
320 static int xenon_emmc_phy_enable_dll(struct sdhci_host *host)
323 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
328 if (WARN_ON(host->clock <= MMC_HIGH_52_MAX_DTR))
331 reg = sdhci_readl(host, phy_regs->dll_ctrl);
336 reg = sdhci_readl(host, phy_regs->dll_ctrl);
353 sdhci_writel(host, reg, phy_regs->dll_ctrl);
360 if (sdhci_readw(host, XENON_SLOT_EXT_PRESENT_STATE) &
364 dev_err(mmc_dev(host->mmc), "Wait for DLL Lock time-out\n");
376 static int xenon_emmc_phy_config_tuning(struct sdhci_host *host)
378 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
384 if (host->clock <= MMC_HIGH_52_MAX_DTR)
387 ret = xenon_emmc_phy_enable_dll(host);
392 reg = sdhci_readl(host, XENON_SLOT_DLL_CUR_DLY_VAL);
395 dev_warn(mmc_dev(host->mmc),
402 reg = sdhci_readl(host, XENON_SLOT_OP_STATUS_CTRL);
408 sdhci_writel(host, reg, XENON_SLOT_OP_STATUS_CTRL);
413 static void xenon_emmc_phy_disable_strobe(struct sdhci_host *host)
415 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
420 reg = sdhci_readl(host, XENON_SLOT_EMMC_CTRL);
422 sdhci_writel(host, reg, XENON_SLOT_EMMC_CTRL);
426 reg = sdhci_readl(host, XENON_EMMC_5_0_PHY_PAD_CONTROL);
428 sdhci_writel(host, reg, XENON_EMMC_5_0_PHY_PAD_CONTROL);
430 reg = sdhci_readl(host, XENON_EMMC_PHY_PAD_CONTROL1);
432 sdhci_writel(host, reg, XENON_EMMC_PHY_PAD_CONTROL1);
437 static void xenon_emmc_phy_strobe_delay_adj(struct sdhci_host *host)
439 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
443 if (WARN_ON(host->timing != MMC_TIMING_MMC_HS400))
446 if (host->clock <= MMC_HIGH_52_MAX_DTR)
449 dev_dbg(mmc_dev(host->mmc), "starts HS400 strobe delay adjustment\n");
451 xenon_emmc_phy_enable_dll(host);
454 reg = sdhci_readl(host, XENON_SLOT_EMMC_CTRL);
463 if (host->mmc->ios.enhanced_strobe)
465 sdhci_writel(host, reg, XENON_SLOT_EMMC_CTRL);
469 reg = sdhci_readl(host, XENON_EMMC_5_0_PHY_PAD_CONTROL);
472 sdhci_writel(host, reg, XENON_EMMC_5_0_PHY_PAD_CONTROL);
474 reg = sdhci_readl(host, XENON_EMMC_PHY_PAD_CONTROL1);
477 sdhci_writel(host, reg, XENON_EMMC_PHY_PAD_CONTROL1);
489 static bool xenon_emmc_phy_slow_mode(struct sdhci_host *host,
492 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
499 if (host->clock > MMC_HIGH_52_MAX_DTR)
502 reg = sdhci_readl(host, phy_regs->timing_adj);
536 sdhci_writel(host, reg, phy_regs->timing_adj);
544 static void xenon_emmc_phy_set(struct sdhci_host *host,
548 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
553 dev_dbg(mmc_dev(host->mmc), "eMMC PHY setting starts\n");
556 reg = sdhci_readl(host, phy_regs->pad_ctrl);
561 sdhci_writel(host, reg, phy_regs->pad_ctrl);
565 reg = sdhci_readl(host, XENON_EMMC_5_0_PHY_PAD_CONTROL);
568 sdhci_writel(host, reg, XENON_EMMC_5_0_PHY_PAD_CONTROL);
570 reg = sdhci_readl(host, XENON_EMMC_PHY_PAD_CONTROL1);
573 sdhci_writel(host, reg, XENON_EMMC_PHY_PAD_CONTROL1);
577 xenon_emmc_phy_slow_mode(host, timing);
585 reg = sdhci_readl(host, phy_regs->timing_adj);
590 sdhci_writel(host, reg, phy_regs->timing_adj);
592 if (xenon_emmc_phy_slow_mode(host, timing))
600 reg = sdhci_readl(host, phy_regs->pad_ctrl2);
603 sdhci_writel(host, reg, phy_regs->pad_ctrl2);
609 reg = sdhci_readl(host, SDHCI_CLOCK_CONTROL);
611 sdhci_writew(host, reg, SDHCI_CLOCK_CONTROL);
613 reg = sdhci_readl(host, phy_regs->func_ctrl);
630 sdhci_writel(host, reg, phy_regs->func_ctrl);
633 reg = sdhci_readl(host, SDHCI_CLOCK_CONTROL);
635 sdhci_writew(host, reg, SDHCI_CLOCK_CONTROL);
639 sdhci_writel(host, phy_regs->logic_timing_val,
642 xenon_emmc_phy_disable_strobe(host);
645 xenon_emmc_phy_init(host);
647 dev_dbg(mmc_dev(host->mmc), "eMMC PHY setting completes\n");
650 static int get_dt_pad_ctrl_data(struct sdhci_host *host,
664 dev_err(mmc_dev(host->mmc), "Unable to find SoC PAD ctrl register address for %pOFn\n",
669 params->pad_ctrl.reg = devm_ioremap_resource(mmc_dev(host->mmc),
676 dev_err(mmc_dev(host->mmc), "Unable to determine SoC PHY PAD ctrl type\n");
684 dev_err(mmc_dev(host->mmc), "Unsupported SoC PHY PAD ctrl type %s\n",
692 static int xenon_emmc_phy_parse_param_dt(struct sdhci_host *host,
720 return get_dt_pad_ctrl_data(host, np, params);
724 void xenon_soc_pad_ctrl(struct sdhci_host *host,
727 xenon_emmc_phy_set_soc_pad(host, signal_voltage);
735 static int xenon_hs_delay_adj(struct sdhci_host *host)
739 if (WARN_ON(host->clock <= XENON_DEFAULT_SDCLK_FREQ))
742 switch (host->timing) {
744 xenon_emmc_phy_strobe_delay_adj(host);
748 return xenon_emmc_phy_config_tuning(host);
754 * It is hard to implement such a scan in host driver
755 * since initiating commands by host driver is not safe.
762 dev_warn_once(mmc_dev(host->mmc), "Timing issue might occur in DDR mode\n");
776 int xenon_phy_adj(struct sdhci_host *host, struct mmc_ios *ios)
778 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
782 if (!host->clock) {
792 if ((host->clock == priv->clock) &&
797 xenon_emmc_phy_set(host, ios->timing);
803 priv->clock = host->clock;
809 if (host->clock > XENON_DEFAULT_SDCLK_FREQ)
810 ret = xenon_hs_delay_adj(host);
814 static int xenon_add_phy(struct device_node *np, struct sdhci_host *host,
817 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
823 dev_err(mmc_dev(host->mmc),
829 ret = xenon_alloc_emmc_phy(host);
833 return xenon_emmc_phy_parse_param_dt(host, np, priv->phy_params);
836 int xenon_phy_parse_dt(struct device_node *np, struct sdhci_host *host)
841 return xenon_add_phy(np, host, phy_type);
843 return xenon_add_phy(np, host, "emmc 5.1 phy");