Lines Matching refs:data
116 * SDMMC hardware data timeout.
1210 struct mmc_request *mrq, u64 *data)
1218 *data |= CQHCI_CMD_TIMING(1);
1246 * command is sent during transfer of last data block which is the
1249 * when data lines are idle.
1280 * HW busy detection timeout is based on programmed data timeout
1544 { .compatible = "nvidia,tegra194-sdhci", .data = &soc_data_tegra194 },
1545 { .compatible = "nvidia,tegra186-sdhci", .data = &soc_data_tegra186 },
1546 { .compatible = "nvidia,tegra210-sdhci", .data = &soc_data_tegra210 },
1547 { .compatible = "nvidia,tegra124-sdhci", .data = &soc_data_tegra124 },
1548 { .compatible = "nvidia,tegra114-sdhci", .data = &soc_data_tegra114 },
1549 { .compatible = "nvidia,tegra30-sdhci", .data = &soc_data_tegra30 },
1550 { .compatible = "nvidia,tegra20-sdhci", .data = &soc_data_tegra20 },
1616 soc_data = match->data;
1669 * data timeout through the bit USE_TMCLK_FOR_DATA_TIMEOUT of
1674 * With TMCLK of 12Mhz provides maximum data timeout period that can
1675 * be achieved is 11s better than using SDCLK for data timeout.