Lines Matching defs:clock
109 * @cur_clk: The index of the current bus clock.
111 * @clk_io: The clock for the internal bus interface.
113 * @clk_bus: The clocks that are available for the SD/MMC bus clock.
114 * @no_divider: No or non-standard internal clock divider.
134 * @no_divider: no or non-standard internal clock divider.
151 * sdhci_s3c_get_max_clk - callback to get maximum clock frequency.
154 * Callback to return the maximum clock rate acheivable by the controller.
174 * @src: The source clock index.
175 * @wanted: The clock frequency wanted.
189 * If controller uses a non-standard clock division, find the best clock
190 * speed possible with selected clock source and skip the division.
218 * sdhci_s3c_set_clock - callback on clock change
220 * @clock: The clock rate being requested.
222 * When the card's clock is going to be changed, look at the new frequency
223 * and find the best clock source to go with it.
225 static void sdhci_s3c_set_clock(struct sdhci_host *host, unsigned int clock)
236 /* don't bother if the clock is going off. */
237 if (clock == 0) {
238 sdhci_set_clock(host, clock);
243 delta = sdhci_s3c_consider_clock(ourhost, src, clock);
251 "selected source %d, clock %d, delta %d\n",
252 best_src, clock, best);
254 /* select the new clock source */
267 /* turn clock off to card before changing clock source */
287 /* reconfigure the controller for new clock rate */
289 if (clock < 25 * 1000000)
293 sdhci_set_clock(host, clock);
297 * sdhci_s3c_get_min_clock - callback to get minimal supported clock value
300 * To init mmc host properly a minimal clock value is needed. For high system
301 * bus clock's values the standard formula gives values out of allowed range.
302 * The clock still can be set to lower values, if clock source other then
322 /* sdhci_cmu_get_max_clk - callback to get maximum clock frequency.*/
344 /* sdhci_cmu_get_min_clock - callback to get minimal supported clock value. */
366 /* sdhci_cmu_set_clock - callback on clock change.*/
367 static void sdhci_cmu_set_clock(struct sdhci_host *host, unsigned int clock)
377 /* If the clock is going off, set to 0 at clock control register */
378 if (clock == 0) {
383 sdhci_s3c_set_clock(host, clock);
390 ret = clk_set_rate(ourhost->clk_bus[ourhost->cur_clk], clock);
392 dev_err(dev, "%s: failed to set clock rate %uHz\n",
393 mmc_hostname(host->mmc), clock);
405 dev_err(dev, "%s: Internal clock never stabilised.\n",
532 dev_err(dev, "failed to get io clock\n");
537 /* enable the local io clock and keep it running for the moment. */
551 dev_info(dev, "clock source %d: %s (%ld Hz)\n",
626 /* HSMMC on Samsung SoCs uses SDCLK as timeout clock */
630 * If controller does not have internal clock divider,