Lines Matching refs:scratch_32
159 u32 scratch_32;
162 O2_SD_PLL_SETTING, &scratch_32);
164 scratch_32 &= 0x0000FFFF;
165 scratch_32 |= value;
168 O2_SD_PLL_SETTING, scratch_32);
238 u32 scratch_32 = 0;
253 scratch_32 = sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1);
254 scratch_32 |= O2_PLL_SOFT_RESET;
255 sdhci_writel(host, scratch_32, O2_PLL_DLL_WDT_CONTROL1);
259 &scratch_32);
261 scratch_32 |= O2_SD_FREG4_ENABLE_CLK_SET;
262 pci_write_config_dword(chip->pdev, O2_SD_FUNC_REG4, scratch_32);
380 u32 scratch_32;
384 O2_SD_FUNC_REG0, &scratch_32);
388 scratch_32 &= ~O2_SD_FREG0_LEDOFF;
390 O2_SD_FUNC_REG0, scratch_32);
393 O2_SD_TEST_REG, &scratch_32);
397 scratch_32 |= O2_SD_LED_ENABLE;
399 O2_SD_TEST_REG, scratch_32);
404 u32 scratch_32;
407 ret = pci_read_config_dword(chip->pdev, O2_SD_DEV_CTRL, &scratch_32);
410 scratch_32 &= ~((1 << 12) | (1 << 13) | (1 << 14));
411 pci_write_config_dword(chip->pdev, O2_SD_DEV_CTRL, scratch_32);
414 ret = pci_read_config_dword(chip->pdev, O2_SD_MISC_REG5, &scratch_32);
417 scratch_32 &= ~((1 << 19) | (1 << 11));
418 scratch_32 |= (1 << 10);
419 pci_write_config_dword(chip->pdev, O2_SD_MISC_REG5, scratch_32);
422 ret = pci_read_config_dword(chip->pdev, O2_SD_TEST_REG, &scratch_32);
425 scratch_32 |= (1 << 4);
426 pci_write_config_dword(chip->pdev, O2_SD_TEST_REG, scratch_32);
432 ret = pci_read_config_dword(chip->pdev, O2_SD_LD0_CTRL, &scratch_32);
435 scratch_32 &= ~(3 << 12);
436 pci_write_config_dword(chip->pdev, O2_SD_LD0_CTRL, scratch_32);
439 ret = pci_read_config_dword(chip->pdev, O2_SD_CAP_REG0, &scratch_32);
442 scratch_32 &= ~(0x01FE);
443 scratch_32 |= 0x00CC;
444 pci_write_config_dword(chip->pdev, O2_SD_CAP_REG0, scratch_32);
447 O2_SD_TUNING_CTRL, &scratch_32);
450 scratch_32 &= ~(0x000000FF);
451 scratch_32 |= 0x00000066;
452 pci_write_config_dword(chip->pdev, O2_SD_TUNING_CTRL, scratch_32);
456 O2_SD_UHS2_L1_CTRL, &scratch_32);
459 scratch_32 &= ~(0x000000FC);
460 scratch_32 |= 0x00000084;
461 pci_write_config_dword(chip->pdev, O2_SD_UHS2_L1_CTRL, scratch_32);
464 ret = pci_read_config_dword(chip->pdev, O2_SD_FUNC_REG3, &scratch_32);
467 scratch_32 &= ~((1 << 21) | (1 << 30));
469 pci_write_config_dword(chip->pdev, O2_SD_FUNC_REG3, scratch_32);
472 ret = pci_read_config_dword(chip->pdev, O2_SD_CAPS, &scratch_32);
475 scratch_32 &= ~(0xf0000000);
476 scratch_32 |= 0x30000000;
477 pci_write_config_dword(chip->pdev, O2_SD_CAPS, scratch_32);
480 O2_SD_MISC_CTRL4, &scratch_32);
483 scratch_32 &= ~(0x000f0000);
484 scratch_32 |= 0x00080000;
485 pci_write_config_dword(chip->pdev, O2_SD_MISC_CTRL4, scratch_32);
528 u32 scratch_32;
545 pci_read_config_dword(chip->pdev, O2_SD_PLL_SETTING, &scratch_32);
547 if ((scratch_32 & 0xFFFF0000) != 0x2c280000)
639 u32 scratch_32;
711 &scratch_32);
712 scratch_32 = ((scratch_32 & 0xFF000000) >> 24);
715 if ((scratch_32 == 0x11) || (scratch_32 == 0x12)) {
716 scratch_32 = 0x25100000;
718 o2_pci_set_baseclk(chip, scratch_32);
721 &scratch_32);
724 scratch_32 |= O2_SD_FREG4_ENABLE_CLK_SET;
727 scratch_32);
742 O2_SD_CLK_SETTING, &scratch_32);
746 scratch_32 &= ~(0xFF00);
747 scratch_32 |= 0x07E0C800;
749 O2_SD_CLK_SETTING, scratch_32);
752 O2_SD_CLKREQ, &scratch_32);
755 scratch_32 |= 0x3;
756 pci_write_config_dword(chip->pdev, O2_SD_CLKREQ, scratch_32);
759 O2_SD_PLL_SETTING, &scratch_32);
763 scratch_32 &= ~(0x1F3F070E);
764 scratch_32 |= 0x18270106;
766 O2_SD_PLL_SETTING, scratch_32);
770 O2_SD_CAP_REG2, &scratch_32);
773 scratch_32 &= ~(0xE0);
775 O2_SD_CAP_REG2, scratch_32);
800 O2_SD_PLL_SETTING, &scratch_32);
802 if ((scratch_32 & 0xff000000) == 0x01000000) {
803 scratch_32 &= 0x0000FFFF;
804 scratch_32 |= 0x1F340000;
807 O2_SD_PLL_SETTING, scratch_32);
809 scratch_32 &= 0x0000FFFF;
810 scratch_32 |= 0x25100000;
813 O2_SD_PLL_SETTING, scratch_32);
817 &scratch_32);
818 scratch_32 |= (1 << 22);
820 O2_SD_FUNC_REG4, scratch_32);
827 pci_read_config_dword(chip->pdev, O2_SD_MISC_CTRL2, &scratch_32);
828 scratch_32 &= 0xFFE7FFFF;
829 scratch_32 |= 0x00180000;
830 pci_write_config_dword(chip->pdev, O2_SD_MISC_CTRL2, scratch_32);