Lines Matching defs:host
11 #include <linux/mmc/host.h>
74 static void sdhci_o2_wait_card_detect_stable(struct sdhci_host *host)
84 scratch32 = sdhci_readl(host, SDHCI_PRESENT_STATE);
91 mmc_hostname(host->mmc));
92 sdhci_dumpregs(host);
99 static void sdhci_o2_enable_internal_clock(struct sdhci_host *host)
106 scratch32 = sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1);
108 sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1);
111 sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1);
115 sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1);
122 scratch = sdhci_readw(host, O2_PLL_DLL_WDT_CONTROL1);
127 mmc_hostname(host->mmc));
128 sdhci_dumpregs(host);
136 sdhci_o2_wait_card_detect_stable(host);
140 scratch32 = sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1);
142 sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1);
147 struct sdhci_host *host = mmc_priv(mmc);
149 if (!(sdhci_readw(host, O2_PLL_DLL_WDT_CONTROL1) & O2_PLL_LOCK_STATUS))
150 sdhci_o2_enable_internal_clock(host);
152 sdhci_o2_wait_card_detect_stable(host);
154 return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
171 static u32 sdhci_o2_pll_dll_wdt_control(struct sdhci_host *host)
173 return sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1);
182 static int sdhci_o2_wait_dll_detect_lock(struct sdhci_host *host)
186 return readx_poll_timeout(sdhci_o2_pll_dll_wdt_control, host,
190 static void sdhci_o2_set_tuning_mode(struct sdhci_host *host)
195 reg = sdhci_readw(host, O2_SD_VENDOR_SETTING);
197 sdhci_writew(host, reg, O2_SD_VENDOR_SETTING);
200 static void __sdhci_o2_execute_tuning(struct sdhci_host *host, u32 opcode)
204 sdhci_send_tuning(host, opcode);
207 u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
211 host->tuning_done = true;
215 mmc_hostname(host->mmc));
223 mmc_hostname(host->mmc));
224 sdhci_reset_tuning(host);
234 static int sdhci_o2_dll_recovery(struct sdhci_host *host)
239 struct sdhci_pci_slot *slot = sdhci_priv(host);
250 sdhci_writeb(host, 0, SDHCI_CLOCK_CONTROL);
253 scratch_32 = sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1);
255 sdhci_writel(host, scratch_32, O2_PLL_DLL_WDT_CONTROL1);
267 sdhci_writeb(host, scratch_8, SDHCI_CLOCK_CONTROL);
269 if (sdhci_o2_get_cd(host->mmc)) {
275 if (sdhci_o2_wait_dll_detect_lock(host)) {
277 sdhci_writeb(host, scratch_8,
282 mmc_hostname(host->mmc),
287 mmc_hostname(host->mmc));
295 mmc_hostname(host->mmc));
306 struct sdhci_host *host = mmc_priv(mmc);
315 if ((host->timing != MMC_TIMING_MMC_HS200) &&
316 (host->timing != MMC_TIMING_UHS_SDR104))
324 scratch = sdhci_readw(host, O2_SD_MISC_CTRL);
326 sdhci_writew(host, scratch, O2_SD_MISC_CTRL);
329 if (readx_poll_timeout(sdhci_o2_pll_dll_wdt_control, host,
332 mmc_hostname(host->mmc));
337 if (!sdhci_o2_wait_dll_detect_lock(host))
338 if (!sdhci_o2_dll_recovery(host)) {
340 mmc_hostname(host->mmc));
344 * o2 sdhci host didn't support 8bit emmc tuning
349 sdhci_set_bus_width(host, MMC_BUS_WIDTH_4);
352 sdhci_o2_set_tuning_mode(host);
354 sdhci_start_tuning(host);
356 __sdhci_o2_execute_tuning(host, opcode);
358 sdhci_end_tuning(host);
362 sdhci_set_bus_width(host, current_bus_width);
366 scratch = sdhci_readw(host, O2_SD_MISC_CTRL);
368 sdhci_writew(host, scratch, O2_SD_MISC_CTRL);
370 sdhci_reset(host, SDHCI_RESET_CMD);
371 sdhci_reset(host, SDHCI_RESET_DATA);
373 host->flags &= ~SDHCI_HS400_TUNING;
382 /* Set led of SD host function enable */
438 /* Set Max power supply capability of SD host */
489 struct sdhci_host *host)
496 mmc_hostname(host->mmc));
504 mmc_hostname(host->mmc), ret);
508 host->irq = pci_irq_vector(chip->pdev, 0);
511 static void sdhci_o2_enable_clk(struct sdhci_host *host, u16 clk)
515 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
517 sdhci_o2_enable_internal_clock(host);
518 if (sdhci_o2_get_cd(host->mmc)) {
520 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
524 static void sdhci_pci_o2_set_clock(struct sdhci_host *host, unsigned int clock)
529 struct sdhci_pci_slot *slot = sdhci_priv(host);
532 host->mmc->actual_clock = 0;
534 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
539 if ((host->timing == MMC_TIMING_UHS_SDR104) && (clock == 200000000)) {
556 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
557 sdhci_o2_enable_clk(host, clk);
563 struct sdhci_host *host;
569 host = slot->host;
572 caps = sdhci_readl(host, SDHCI_CAPABILITIES);
579 host->mmc->caps |= MMC_CAP_8_BIT_DATA;
587 reg = sdhci_readl(host, O2_SD_VENDOR_SETTING);
589 host->quirks |= SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12;
591 sdhci_pci_o2_enable_msi(chip, host);
600 mmc_hostname(host->mmc));
601 host->flags &= ~SDHCI_SIGNALING_330;
602 host->flags |= SDHCI_SIGNALING_180;
603 host->mmc->caps2 |= MMC_CAP2_NO_SD;
604 host->mmc->caps2 |= MMC_CAP2_NO_SDIO;
609 slot->host->mmc_host_ops.get_cd = sdhci_o2_get_cd;
613 slot->host->mmc_host_ops.get_cd = sdhci_o2_get_cd;
614 host->mmc->caps2 |= MMC_CAP2_NO_SDIO;
615 host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN;
618 host->mmc_host_ops.execute_tuning = sdhci_o2_execute_tuning;
623 reg = sdhci_readl(host, O2_SD_VENDOR_SETTING2);
625 sdhci_writel(host, reg, O2_SD_VENDOR_SETTING2);