Lines Matching defs:host
113 static inline void gl9750_wt_on(struct sdhci_host *host)
118 wt_value = sdhci_readl(host, SDHCI_GLI_9750_WT);
127 sdhci_writel(host, wt_value, SDHCI_GLI_9750_WT);
130 static inline void gl9750_wt_off(struct sdhci_host *host)
135 wt_value = sdhci_readl(host, SDHCI_GLI_9750_WT);
144 sdhci_writel(host, wt_value, SDHCI_GLI_9750_WT);
147 static void gli_set_9750(struct sdhci_host *host)
157 gl9750_wt_on(host);
159 driving_value = sdhci_readl(host, SDHCI_GLI_9750_DRIVING);
160 pll_value = sdhci_readl(host, SDHCI_GLI_9750_PLL);
161 sw_ctrl_value = sdhci_readl(host, SDHCI_GLI_9750_SW_CTRL);
162 misc_value = sdhci_readl(host, SDHCI_GLI_9750_MISC);
163 parameter_value = sdhci_readl(host, SDHCI_GLI_9750_TUNING_PARAMETERS);
164 control_value = sdhci_readl(host, SDHCI_GLI_9750_TUNING_CONTROL);
174 sdhci_writel(host, driving_value, SDHCI_GLI_9750_DRIVING);
179 sdhci_writel(host, sw_ctrl_value, SDHCI_GLI_9750_SW_CTRL);
210 sdhci_writel(host, pll_value, SDHCI_GLI_9750_PLL);
211 sdhci_writel(host, misc_value, SDHCI_GLI_9750_MISC);
214 ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
216 sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2);
222 sdhci_writel(host, control_value, SDHCI_GLI_9750_TUNING_CONTROL);
225 sdhci_writel(host, parameter_value, SDHCI_GLI_9750_TUNING_PARAMETERS);
231 sdhci_writel(host, control_value, SDHCI_GLI_9750_TUNING_CONTROL);
234 ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
236 sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2);
238 gl9750_wt_off(host);
241 static void gli_set_9750_rx_inv(struct sdhci_host *host, bool b)
245 gl9750_wt_on(host);
247 misc_value = sdhci_readl(host, SDHCI_GLI_9750_MISC);
256 sdhci_writel(host, misc_value, SDHCI_GLI_9750_MISC);
258 gl9750_wt_off(host);
261 static int __sdhci_execute_tuning_9750(struct sdhci_host *host, u32 opcode)
267 gli_set_9750_rx_inv(host, !!rx_inv);
268 sdhci_start_tuning(host);
273 sdhci_send_tuning(host, opcode);
275 if (!host->tuning_done) {
276 sdhci_abort_tuning(host, opcode);
280 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
288 if (!host->tuning_done) {
290 mmc_hostname(host->mmc));
295 mmc_hostname(host->mmc));
296 sdhci_reset_tuning(host);
301 static int gl9750_execute_tuning(struct sdhci_host *host, u32 opcode)
303 host->mmc->retune_period = 0;
304 if (host->tuning_mode == SDHCI_TUNING_MODE_1)
305 host->mmc->retune_period = host->tuning_count;
307 gli_set_9750(host);
308 host->tuning_err = __sdhci_execute_tuning_9750(host, opcode);
309 sdhci_end_tuning(host);
314 static void gl9750_disable_ssc_pll(struct sdhci_host *host)
318 gl9750_wt_on(host);
319 pll = sdhci_readl(host, SDHCI_GLI_9750_PLL);
321 sdhci_writel(host, pll, SDHCI_GLI_9750_PLL);
322 gl9750_wt_off(host);
325 static void gl9750_set_pll(struct sdhci_host *host, u8 dir, u16 ldiv, u8 pdiv)
329 gl9750_wt_on(host);
330 pll = sdhci_readl(host, SDHCI_GLI_9750_PLL);
337 sdhci_writel(host, pll, SDHCI_GLI_9750_PLL);
338 gl9750_wt_off(host);
344 static void gl9750_set_ssc(struct sdhci_host *host, u8 enable, u8 step, u16 ppm)
349 gl9750_wt_on(host);
350 pll = sdhci_readl(host, SDHCI_GLI_9750_PLL);
351 ssc = sdhci_readl(host, SDHCI_GLI_9750_PLLSSC);
358 sdhci_writel(host, ssc, SDHCI_GLI_9750_PLLSSC);
359 sdhci_writel(host, pll, SDHCI_GLI_9750_PLL);
360 gl9750_wt_off(host);
363 static void gl9750_set_ssc_pll_205mhz(struct sdhci_host *host)
366 gl9750_set_ssc(host, 0x1, 0x1F, 0xFFE7);
367 gl9750_set_pll(host, 0x1, 0x246, 0x0);
370 static void sdhci_gl9750_set_clock(struct sdhci_host *host, unsigned int clock)
372 struct mmc_ios *ios = &host->mmc->ios;
375 host->mmc->actual_clock = 0;
377 gl9750_disable_ssc_pll(host);
378 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
383 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
385 host->mmc->actual_clock = 205000000;
386 gl9750_set_ssc_pll_205mhz(host);
389 sdhci_enable_clk(host, clk);
400 mmc_hostname(slot->host->mmc), ret);
404 slot->host->irq = pci_irq_vector(slot->chip->pdev, 0);
497 static void sdhci_gl9755_set_clock(struct sdhci_host *host, unsigned int clock)
499 struct sdhci_pci_slot *slot = sdhci_priv(host);
500 struct mmc_ios *ios = &host->mmc->ios;
505 host->mmc->actual_clock = 0;
508 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
513 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
515 host->mmc->actual_clock = 205000000;
519 sdhci_enable_clk(host, clk);
524 struct sdhci_host *host = slot->host;
527 slot->host->mmc->caps2 |= MMC_CAP2_NO_SDIO;
528 sdhci_enable_v4_mode(host);
535 struct sdhci_host *host = slot->host;
538 slot->host->mmc->caps2 |= MMC_CAP2_NO_SDIO;
539 sdhci_enable_v4_mode(host);
544 static void sdhci_gli_voltage_switch(struct sdhci_host *host)
567 static void sdhci_gl9750_reset(struct sdhci_host *host, u8 mask)
569 sdhci_reset(host, mask);
570 gli_set_9750(host);
573 static u32 sdhci_gl9750_readl(struct sdhci_host *host, int reg)
577 value = readl(host->ioaddr + reg);
604 return cqhci_resume(slot->host->mmc);
612 ret = cqhci_suspend(slot->host->mmc);
616 return sdhci_suspend_host(slot->host);
623 struct sdhci_host *host = mmc_priv(mmc);
626 val = sdhci_readl(host, SDHCI_GLI_9763E_HS400_ES_REG);
632 sdhci_writel(host, val, SDHCI_GLI_9763E_HS400_ES_REG);
635 static void sdhci_set_gl9763e_signaling(struct sdhci_host *host,
640 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
651 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
671 struct sdhci_host *host = mmc_priv(mmc);
673 sdhci_writew(host, GLI_9763E_CQE_TRNS_MODE, SDHCI_TRANSFER_MODE);
677 static u32 sdhci_gl9763e_cqhci_irq(struct sdhci_host *host, u32 intmask)
682 if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error))
685 cqhci_irq(host->mmc, intmask, cmd_error, data_error);
692 struct sdhci_host *host = mmc_priv(mmc);
699 sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE);
713 struct sdhci_host *host = slot->host;
718 ret = sdhci_setup_host(host);
728 cq_host->mmio = host->ioaddr + SDHCI_GLI_9763E_CQE_BASE_ADDR;
731 dma64 = host->flags & SDHCI_USE_64_BIT_DMA;
735 ret = cqhci_init(cq_host, host->mmc, dma64);
739 ret = __sdhci_add_host(host);
746 sdhci_cleanup_host(host);
750 static void sdhci_gl9763e_reset(struct sdhci_host *host, u8 mask)
752 if ((host->mmc->caps2 & MMC_CAP2_CQE) && (mask & SDHCI_RESET_ALL) &&
753 host->mmc->cqe_private)
754 cqhci_deactivate(host->mmc);
755 sdhci_reset(host, mask);
781 struct sdhci_host *host = slot->host;
784 host->mmc->caps |= MMC_CAP_8_BIT_DATA |
787 host->mmc->caps2 |= MMC_CAP2_HS200_1_8V_SDR |
795 host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD;
798 host->mmc_host_ops.hs400_enhanced_strobe =
801 sdhci_enable_v4_mode(host);