Lines Matching refs:state
587 dev_err(dev, "failed to select pinctrl state\n");
977 dev_err(dev, "no pinctrl state for %s mode", mode);
993 struct pinctrl_state *state;
1012 state = pinctrl_lookup_state(omap_host->pinctrl, "default");
1013 if (IS_ERR(state)) {
1014 dev_err(dev, "no pinctrl state for default mode\n");
1015 return PTR_ERR(state);
1017 pinctrl_state[MMC_TIMING_LEGACY] = state;
1019 state = sdhci_omap_iodelay_pinctrl_state(omap_host, "sdr104", caps,
1021 if (!IS_ERR(state))
1022 pinctrl_state[MMC_TIMING_UHS_SDR104] = state;
1024 state = sdhci_omap_iodelay_pinctrl_state(omap_host, "ddr50", caps,
1026 if (!IS_ERR(state))
1027 pinctrl_state[MMC_TIMING_UHS_DDR50] = state;
1029 state = sdhci_omap_iodelay_pinctrl_state(omap_host, "sdr50", caps,
1031 if (!IS_ERR(state))
1032 pinctrl_state[MMC_TIMING_UHS_SDR50] = state;
1034 state = sdhci_omap_iodelay_pinctrl_state(omap_host, "sdr25", caps,
1036 if (!IS_ERR(state))
1037 pinctrl_state[MMC_TIMING_UHS_SDR25] = state;
1039 state = sdhci_omap_iodelay_pinctrl_state(omap_host, "sdr12", caps,
1041 if (!IS_ERR(state))
1042 pinctrl_state[MMC_TIMING_UHS_SDR12] = state;
1044 state = sdhci_omap_iodelay_pinctrl_state(omap_host, "ddr_1_8v", caps,
1046 if (!IS_ERR(state)) {
1047 pinctrl_state[MMC_TIMING_MMC_DDR52] = state;
1049 state = sdhci_omap_iodelay_pinctrl_state(omap_host, "ddr_3_3v",
1052 if (!IS_ERR(state))
1053 pinctrl_state[MMC_TIMING_MMC_DDR52] = state;
1056 state = sdhci_omap_iodelay_pinctrl_state(omap_host, "hs", caps,
1058 if (!IS_ERR(state))
1059 pinctrl_state[MMC_TIMING_SD_HS] = state;
1061 state = sdhci_omap_iodelay_pinctrl_state(omap_host, "hs", caps,
1063 if (!IS_ERR(state))
1064 pinctrl_state[MMC_TIMING_MMC_HS] = state;
1066 state = sdhci_omap_iodelay_pinctrl_state(omap_host, "hs200_1_8v", caps2,
1068 if (!IS_ERR(state))
1069 pinctrl_state[MMC_TIMING_MMC_HS200] = state;